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| author | Simon Dardis <simon.dardis@imgtec.com> | 2016-08-24 13:00:47 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-08-24 13:00:47 +0000 |
| commit | f114820912b8484a9b40429dd58dd829a87d8c58 (patch) | |
| tree | be69ca39d7d8c08ea7eeefffca70969016558f84 /llvm/test/CodeGen/Mips/llvm-ir/and.ll | |
| parent | 7a50c8c2ba58beaa70879d22c628ebd213fcf4ee (diff) | |
| download | bcm5719-llvm-f114820912b8484a9b40429dd58dd829a87d8c58.tar.gz bcm5719-llvm-f114820912b8484a9b40429dd58dd829a87d8c58.zip | |
[mips] Preparatory work for a generic scheduler
Extend instruction definitions from nearly all ISAs to include
appropriate instruction itineraries. Change MIPS16s gp prologue
generation to use real instructions instead of using a pseudo
instruction.
Reviewers: dsanders, vkalintiris
Differential Review: https://reviews.llvm.org/D23548
llvm-svn: 279623
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir/and.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/and.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll index 40137bc4766..c94f98467ca 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll @@ -131,13 +131,13 @@ entry: ; GP64: and $2, $4, $6 ; GP64: and $3, $5, $7 - ; MM32: lw $[[T0:[0-9]+]], 20($sp) - ; MM32: lw $[[T1:[0-9]+]], 16($sp) - ; MM32: and16 $[[T1]], $4 - ; MM32: and16 $[[T0]], $5 + ; MM32: lw $[[T0:[0-9]+]], 32($sp) + ; MM32: lw $[[T1:[0-9]+]], 28($sp) ; MM32: lw $[[T2:[0-9]+]], 24($sp) - ; MM32: and16 $[[T2]], $6 - ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: and16 $[[T2]], $4 + ; MM32: and16 $[[T1]], $5 + ; MM32: and16 $[[T0]], $6 + ; MM32: lw $[[T3:[0-9]+]], 36($sp) ; MM32: and16 $[[T3]], $7 ; MM64: and $2, $4, $6 |
