[mips] Preparatory work for a generic scheduler

Extend instruction definitions from nearly all ISAs to include
appropriate instruction itineraries. Change MIPS16s gp prologue
generation to use real instructions instead of using a pseudo
instruction.

Reviewers: dsanders, vkalintiris

Differential Review: https://reviews.llvm.org/D23548

llvm-svn: 279623

15 files changed, 63 insertions, 63 deletions

diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
index 756e5fe29bf..f775a895328 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
@@ -154,13 +154,13 @@ entry:
   ; MM32:       lw        $[[T3:[0-9]+]], 24($sp)
   ; MM32:       addu      $[[T4:[0-9]+]], $[[T2]], $[[T3]]
   ; MM32:       addu      $[[T5:[0-9]+]], $6, $[[T4]]
-  ; MM32:       sltu      $[[T6:[0-9]+]], $[[T5]], $[[T3]]
+  ; MM32:       lw        $[[T6:[0-9]+]], 16($sp)
   ; MM32:       lw        $[[T7:[0-9]+]], 20($sp)
-  ; MM32:       addu      $[[T8:[0-9]+]], $[[T6]], $[[T7]]
-  ; MM32:       addu      $[[T9:[0-9]+]], $5, $[[T8]]
-  ; MM32:       lw        $[[T10:[0-9]+]], 16($sp)
-  ; MM32:       sltu      $[[T11:[0-9]+]], $[[T9]], $[[T7]]
-  ; MM32:       addu      $[[T12:[0-9]+]], $[[T11]], $[[T10]]
+  ; MM32:       sltu      $[[T8:[0-9]+]], $[[T5]], $[[T3]]
+  ; MM32:       addu      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+  ; MM32:       addu      $[[T10:[0-9]+]], $5, $[[T9]]
+  ; MM32:       sltu      $[[T11:[0-6]+]], $[[T9]], $[[T7]]
+  ; MM32:       addu      $[[T12:[0-6]+]], $[[T11]], $[[T6]]
   ; MM32:       addu      $[[T13:[0-9]+]], $4, $[[T12]]
   ; MM32:       move      $4, $[[T5]]
   ; MM32:       move      $5, $[[T1]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
index 40137bc4766..c94f98467ca 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll
@@ -131,13 +131,13 @@ entry:
   ; GP64:         and     $2, $4, $6
   ; GP64:         and     $3, $5, $7
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
-  ; MM32:         and16   $[[T1]], $4
-  ; MM32:         and16   $[[T0]], $5
+  ; MM32:         lw      $[[T0:[0-9]+]], 32($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 28($sp)
   ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
-  ; MM32:         and16   $[[T2]], $6
-  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         and16   $[[T2]], $4
+  ; MM32:         and16   $[[T1]], $5
+  ; MM32:         and16   $[[T0]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 36($sp)
   ; MM32:         and16   $[[T3]], $7
 
   ; MM64:         and     $2, $4, $6
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
index cfb9855e643..0621ecd3a3d 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -129,9 +129,9 @@ entry:
   ; GP64:       dsrav     $2, $4, $5
 
   ; MMR3:       srlv      $[[T0:[0-9]+]], $5, $7
-  ; MMR3:       sll16     $[[T1:[0-9]+]], $4, 1
-  ; MMR3:       not16     $[[T2:[0-9]+]], $7
-  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       not16     $[[T1:[0-9]+]], $7
+  ; MMR3:       sll16     $[[T2:[0-9]+]], $4, 1
+  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR3:       srav      $[[T5:[0-9]+]], $4, $7
   ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
@@ -146,9 +146,9 @@ entry:
   ; MMR6:       selnez    $[[T4:[0-9]+]], $[[T3]], $[[T1]]
   ; MMR6:       or        $[[T5:[0-9]+]], $[[T4]], $[[T2]]
   ; MMR6:       srlv      $[[T6:[0-9]+]], $5, $7
-  ; MMR6:       sll16     $[[T7:[0-9]+]], $4, 1
-  ; MMR6:       not16     $[[T8:[0-9]+]], $7
-  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T7]], $[[T8]]
+  ; MMR6:       not16     $[[T7:[0-9]+]], $7
+  ; MMR6:       sll16     $[[T8:[0-9]+]], $4, 1
+  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
   ; MMR6:       or16      $[[T10:[0-9]+]], $[[T6]]
   ; MMR6:       seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
   ; MMR6:       selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
index ba124b0f467..b8d908ae35e 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -123,9 +123,9 @@ entry:
   ; GP64:         dsrlv   $2, $4, $5
 
   ; MMR3:       srlv      $[[T0:[0-9]+]], $5, $7
-  ; MMR3:       sll16     $[[T1:[0-9]+]], $4, 1
-  ; MMR3:       not16     $[[T2:[0-9]+]], $7
-  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       not16     $[[T1:[0-9]+]], $7
+  ; MMR3:       sll16     $[[T2:[0-9]+]], $4, 1
+  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR3:       srlv      $[[T5:[0-9]+]], $4, $7
   ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
@@ -134,9 +134,9 @@ entry:
   ; MMR3:       movn      $2, $[[T8]], $[[T6]]
 
   ; MMR6:       srlv      $[[T0:[0-9]+]], $5, $7
-  ; MMR6:       sll16     $[[T1:[0-9]+]], $4, 1
-  ; MMR6:       not16     $[[T2:[0-9]+]], $7
-  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR6:       not16     $[[T1:[0-9]+]], $7
+  ; MMR6:       sll16     $[[T2:[0-9]+]], $4, 1
+  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
   ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
index 8d63e496806..4236bdfc8c0 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -247,7 +247,7 @@ entry:
   ; 64R6:           daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
 
-  ; MM32:           lw      $25, %call16(__multi3)($2)
+  ; MM32:           lw      $25, %call16(__multi3)($16)
 
   %r = mul i128 %a, %b
   ret i128 %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/not.ll b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
index 5f7374f6dfb..e8cb5cebb67 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/not.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/not.ll
@@ -221,12 +221,12 @@ entry:
   ; GP64:         nor     $2, $6, $4
   ; GP64:         nor     $3, $7, $5
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
-  ; MM32:         nor     $2, $[[T1]], $4
-  ; MM32:         nor     $3, $[[T0]], $5
-  ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
-  ; MM32:         nor     $4, $[[T2]], $6
+  ; MM32:         lw      $[[T0:[0-9]+]], 24($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 20($sp)
+  ; MM32:         lw      $[[T2:[0-9]+]], 16($sp)
+  ; MM32:         nor     $2, $[[T2]], $4
+  ; MM32:         nor     $3, $[[T1]], $5
+  ; MM32:         nor     $4, $[[T0]], $6
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         nor     $5, $[[T3]], $7
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/or.ll b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
index 192e5de6230..9d4abc83d68 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/or.ll
@@ -119,13 +119,13 @@ entry:
   ; GP64:         or      $2, $4, $6
   ; GP64:         or      $3, $5, $7
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
-  ; MM32:         or16    $[[T1]], $4
-  ; MM32:         or16    $[[T0]], $5
+  ; MM32:         lw      $[[T0:[0-9]+]], 32($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 28($sp)
   ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
-  ; MM32:         or16    $[[T2]], $6
-  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         or16    $[[T2]], $4
+  ; MM32:         or16    $[[T1]], $5
+  ; MM32:         or16    $[[T0]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 36($sp)
   ; MM32:         or16    $[[T3]], $7
 
   ; MM64:         or      $2, $4, $6
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
index 2d2b8ff12c0..0bbdae8f5e2 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
@@ -188,7 +188,7 @@ entry:
   ; GP64-NOT-R6:  ld      $25, %call16(__divti3)($gp)
   ; 64R6:         ld      $25, %call16(__divti3)($gp)
 
-  ; MM32:         lw      $25, %call16(__divti3)($2)
+  ; MM32:         lw      $25, %call16(__divti3)($16)
 
   ; MM64:         ld      $25, %call16(__divti3)($2)
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
index 213a6b1a06f..11df5644e60 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -198,13 +198,13 @@ entry:
   ; MM32R3:     movn    $3, $7, $[[T0]]
 
   ; MM32R6:     andi16  $[[T0:[0-9]+]], $4, 1
-  ; MM32R6:     lw      $[[T1:[0-9]+]], 16($sp)
-  ; MM32R6:     seleqz  $[[T2:[0-9]+]], $[[T1]], $[[T0]]
-  ; MM32R6:     selnez  $[[T3:[0-9]+]], $6, $[[T0]]
-  ; MM32R6:     or      $2, $[[T3]], $[[T2]]
+  ; MM32R6:     selnez  $[[T1:[0-9]+]], $6, $[[T0]]
+  ; MM32R6:     lw      $[[T2:[0-9]+]], 16($sp)
+  ; MM32R6:     seleqz  $[[T3:[0-9]+]], $[[T2]], $[[T0]]
+  ; MM32R6:     or      $2, $[[T1]], $[[T3]]
+  ; MM32R6:     selnez  $[[T6:[0-9]+]], $7, $[[T0]]
   ; MM32R6:     lw      $[[T4:[0-9]+]], 20($sp)
   ; MM32R6:     seleqz  $[[T5:[0-9]+]], $[[T4]], $[[T0]]
-  ; MM32R6:     selnez  $[[T6:[0-9]+]], $7, $[[T0]]
   ; MM32R6:     or      $3, $[[T6]], $[[T5]]
 
   %r = select i1 %s, i64 %x, i64 %y
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
index 20267fd0686..6517a0f282b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -139,9 +139,9 @@ entry:
   ; GP64:       dsllv     $2, $4, $5
 
   ; MMR3:       sllv      $[[T0:[0-9]+]], $4, $7
-  ; MMR3:       srl16     $[[T1:[0-9]+]], $5, 1
-  ; MMR3:       not16     $[[T2:[0-9]+]], $7
-  ; MMR3:       srlv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       not16     $[[T1:[0-9]+]], $7
+  ; MMR3:       srl16     $[[T2:[0-9]+]], $5, 1
+  ; MMR3:       srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR3:       sllv      $[[T5:[0-9]+]], $5, $7
   ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
@@ -150,9 +150,9 @@ entry:
   ; MMR3:       movn      $3, $[[T8]], $[[T6]]
 
   ; MMR6:       sllv      $[[T0:[0-9]+]], $4, $7
-  ; MMR6:       srl16     $[[T1:[0-9]+]], $5, 1
-  ; MMR6:       not16     $[[T2:[0-9]+]], $7
-  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR6:       not16     $[[T1:[0-9]+]], $7
+  ; MMR6:       srl16     $[[T2:[0-9]+]], $5, 1
+  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
   ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
   ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
   ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
index 3431922b6c5..f67477e6093 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll
@@ -180,7 +180,7 @@ entry:
   ; GP64-NOT-R6:  ld      $25, %call16(__modti3)($gp)
   ; 64R6:         ld      $25, %call16(__modti3)($gp)
 
-  ; MM32:         lw      $25, %call16(__modti3)($2)
+  ; MM32:         lw      $25, %call16(__modti3)($16)
 
   ; MM64:         ld      $25, %call16(__modti3)($2)
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
index 33757657ad9..747a9eb3db3 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -134,16 +134,16 @@ entry:
   ; GP32-MM:        sltu      $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
   ; GP32-MM:        lw        $[[T3:[0-9]+]], 16($sp)
   ; GP32-MM:        addu      $[[T3]], $[[T1]], $[[T3]]
+  ; GP32-MM:        lw        $[[T5:[0-9]+]], 24($sp)
   ; GP32-MM:        lw        $[[T4:[0-9]+]], 28($sp)
   ; GP32-MM:        subu      $[[T1]], $7, $[[T4]]
-  ; GP32-MM:        subu      $[[T3]], $[[T5:[0-9]+]], $[[T3]]
-  ; GP32-MM:        lw        $[[T5]], 24($sp)
+  ; GP32-MM:        subu      $[[T3]], $4, $[[T3]]
   ; GP32-MM:        sltu      $[[T6:[0-9]+]], $6, $[[T5]]
   ; GP32-MM:        addu      $[[T0]], $[[T6]], $[[T0]]
   ; GP32-MM:        subu      $[[T0]], $5, $[[T0]]
-  ; GP32-MM:        sltu      $[[T2]], $7, $[[T4]]
-  ; GP32-MM:        addu      $[[T5]], $[[T2]], $[[T5]]
-  ; GP32-MM:        subu      $[[T5]], $6, $[[T5]]
+  ; GP32-MM:        sltu      $[[T7:[0-9]+]], $7, $[[T4]]
+  ; GP32-MM:        addu      $[[T8:[0-8]+]], $[[T7]], $[[T5]]
+  ; GP32-MM:        subu      $[[T9:[0-9]+]], $6, $[[T8]]
   ; GP32-MM:        move      $[[T2]], $[[T1]]
 
   ; GP64:           dsubu     $3, $5, $7
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
index 6f4dcb5d7bb..78ab36442a9 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -152,7 +152,7 @@ entry:
   ; GP64-NOT-R6:  ld      $25, %call16(__udivti3)($gp)
   ; 64-R6:        ld      $25, %call16(__udivti3)($gp)
 
-  ; MM32:         lw      $25, %call16(__udivti3)($2)
+  ; MM32:         lw      $25, %call16(__udivti3)($16)
 
   ; MM64:         ld      $25, %call16(__udivti3)($2)
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
index 69b13ba7fee..bad7c507b05 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll
@@ -208,7 +208,7 @@ entry:
   ; GP64-NOT-R6:  ld      $25, %call16(__umodti3)($gp)
   ; 64R6:         ld      $25, %call16(__umodti3)($gp)
 
-  ; MM32:         lw      $25, %call16(__umodti3)($2)
+  ; MM32:         lw      $25, %call16(__umodti3)($16)
 
   ; MM64:         ld      $25, %call16(__umodti3)($2)
 
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
index 0ba696fbc33..cfc12e23d6c 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -129,13 +129,13 @@ entry:
   ; GP64:         xor     $2, $4, $6
   ; GP64:         xor     $3, $5, $7
 
-  ; MM32:         lw      $[[T0:[0-9]+]], 20($sp)
-  ; MM32:         lw      $[[T1:[0-9]+]], 16($sp)
-  ; MM32:         xor16   $[[T1]], $4
-  ; MM32:         xor16   $[[T0]], $5
+  ; MM32:         lw      $[[T0:[0-9]+]], 32($sp)
+  ; MM32:         lw      $[[T1:[0-9]+]], 28($sp)
   ; MM32:         lw      $[[T2:[0-9]+]], 24($sp)
-  ; MM32:         xor16   $[[T2]], $6
-  ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
+  ; MM32:         xor16   $[[T2]], $4
+  ; MM32:         xor16   $[[T1]], $5
+  ; MM32:         xor16   $[[T0]], $6
+  ; MM32:         lw      $[[T3:[0-9]+]], 36($sp)
   ; MM32:         xor16   $[[T3]], $7
 
   ; MM64:         xor     $2, $4, $6