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authorSimon Dardis <simon.dardis@imgtec.com>2016-08-24 13:00:47 +0000
committerSimon Dardis <simon.dardis@imgtec.com>2016-08-24 13:00:47 +0000
commitf114820912b8484a9b40429dd58dd829a87d8c58 (patch)
treebe69ca39d7d8c08ea7eeefffca70969016558f84 /llvm/test/CodeGen/Mips/llvm-ir/add.ll
parent7a50c8c2ba58beaa70879d22c628ebd213fcf4ee (diff)
downloadbcm5719-llvm-f114820912b8484a9b40429dd58dd829a87d8c58.tar.gz
bcm5719-llvm-f114820912b8484a9b40429dd58dd829a87d8c58.zip
[mips] Preparatory work for a generic scheduler
Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 llvm-svn: 279623
Diffstat (limited to 'llvm/test/CodeGen/Mips/llvm-ir/add.ll')
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/add.ll12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/add.ll b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
index 756e5fe29bf..f775a895328 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/add.ll
@@ -154,13 +154,13 @@ entry:
; MM32: lw $[[T3:[0-9]+]], 24($sp)
; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]]
- ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
+ ; MM32: lw $[[T6:[0-9]+]], 16($sp)
; MM32: lw $[[T7:[0-9]+]], 20($sp)
- ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
- ; MM32: addu $[[T9:[0-9]+]], $5, $[[T8]]
- ; MM32: lw $[[T10:[0-9]+]], 16($sp)
- ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]]
- ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T10]]
+ ; MM32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
+ ; MM32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+ ; MM32: addu $[[T10:[0-9]+]], $5, $[[T9]]
+ ; MM32: sltu $[[T11:[0-6]+]], $[[T9]], $[[T7]]
+ ; MM32: addu $[[T12:[0-6]+]], $[[T11]], $[[T6]]
; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]]
; MM32: move $4, $[[T5]]
; MM32: move $5, $[[T1]]
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