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| author | Puyan Lotfi <puyan@puyan.org> | 2018-01-31 22:04:26 +0000 |
|---|---|---|
| committer | Puyan Lotfi <puyan@puyan.org> | 2018-01-31 22:04:26 +0000 |
| commit | 43e94b15ea0c180ebb0fd3e6b697dac4564aaf60 (patch) | |
| tree | f7934a17bdee8aeebc4f8c00769b5fdd6bd1b9ff /llvm/test/CodeGen/Mips/instverify | |
| parent | de07acb9a53066cb9c2a3e4bc4edd7be06db17d1 (diff) | |
| download | bcm5719-llvm-43e94b15ea0c180ebb0fd3e6b697dac4564aaf60.tar.gz bcm5719-llvm-43e94b15ea0c180ebb0fd3e6b697dac4564aaf60.zip | |
Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html
In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.
llvm-svn: 323922
Diffstat (limited to 'llvm/test/CodeGen/Mips/instverify')
24 files changed, 126 insertions, 126 deletions
diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir index 8e3b887ffe9..d9d7f9a777f 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXT %0, 55, 10 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir index 968dd4e370f..f20677d9ec4 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXT %0, 5, 50 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir index bdf82ecd0d6..a25f25e42e2 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXTM %0, 3, 62 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir index 987a228a1f8..3f9c2bdff3f 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXTM %0, 65, 5 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir index b1e367e027e..823519f3e55 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXTM %0, 31, 67 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir index 9b6dac08350..e62904ce5f8 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXTU %0, 43, 30 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir index 65e5bd0e1c1..ed0a8747a8b 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXTU %0, 64, 5 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir index 8c548f1c7b4..f1d038739d5 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXTU %0, 63, 1 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir index 0511d1ae09d..927862ed394 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DEXTU %0, 33, 67 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir index d1d178575c8..c2f1b89bec8 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINS %0, 17, 17 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir index 1602aa2e25a..6203b87bb21 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINS %0, 55, 10 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir index bf713bf992f..d69136ca4e2 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINS %0, 5, 50 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir index aa73e7f1a53..7cc6c2e1aef 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINSM %0, 20, 50 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir index 66a6053ca74..54c55cee97e 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINSM %0, 65, 5 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir index fba3bee969a..fd18417591a 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINSM %0, 31, 67 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir index 9d2d17c3c18..015380951d0 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINSU %0, 50, 20 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir index d89bb2de3ae..b9b88a9fd42 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINSU %0, 65, 5 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir index 550f890fbd8..99aee894815 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr64, preferred-register: '' } - { id: 1, class: gpr64, preferred-register: '' } liveins: - - { reg: '%a0_64', virtual-reg: '%0' } + - { reg: '$a0_64', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0_64 + liveins: $a0_64 - %0 = COPY %a0_64 + %0 = COPY $a0_64 %1 = DINSU %0, 33, 67 - %v0_64 = COPY %1 - RetRA implicit %v0_64 + $v0_64 = COPY %1 + RetRA implicit $v0_64 ... diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir index 94edecd8d24..c10fe557608 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr32, preferred-register: '' } - { id: 1, class: gpr32, preferred-register: '' } liveins: - - { reg: '%a0', virtual-reg: '%0' } + - { reg: '$a0', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0 + liveins: $a0 - %0 = COPY %a0 + %0 = COPY $a0 %1 = EXT %0, 17, 17 - %v0 = COPY %1 - RetRA implicit %v0 + $v0 = COPY %1 + RetRA implicit $v0 ... diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir index 7cca1b6a1b3..39a81a6b58b 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr32, preferred-register: '' } - { id: 1, class: gpr32, preferred-register: '' } liveins: - - { reg: '%a0', virtual-reg: '%0' } + - { reg: '$a0', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0 + liveins: $a0 - %0 = COPY %a0 + %0 = COPY $a0 %1 = EXT %0, 44, 21 - %v0 = COPY %1 - RetRA implicit %v0 + $v0 = COPY %1 + RetRA implicit $v0 ... diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir index 4c35e1fb6a0..ad6653ca8cb 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir @@ -16,7 +16,7 @@ registers: - { id: 0, class: gpr32, preferred-register: '' } - { id: 1, class: gpr32, preferred-register: '' } liveins: - - { reg: '%a0', virtual-reg: '%0' } + - { reg: '$a0', virtual-reg: '%0' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -39,11 +39,11 @@ stack: constants: body: | bb.0.entry: - liveins: %a0 + liveins: $a0 - %0 = COPY %a0 + %0 = COPY $a0 %1 = EXT %0, 0, 33 - %v0 = COPY %1 - RetRA implicit %v0 + $v0 = COPY %1 + RetRA implicit $v0 ... diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir index e825b5997d8..f8266f0f571 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -18,8 +18,8 @@ registers: - { id: 2, class: gpr32, preferred-register: '' } - { id: 3, class: gpr32, preferred-register: '' } liveins: - - { reg: '%a0', virtual-reg: '%0' } - - { reg: '%a1', virtual-reg: '%1' } + - { reg: '$a0', virtual-reg: '%0' } + - { reg: '$a1', virtual-reg: '%1' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -42,13 +42,13 @@ stack: constants: body: | bb.0.entry: - liveins: %a0, %a1 + liveins: $a0, $a1 - %1 = COPY %a1 - %0 = COPY %a0 + %1 = COPY $a1 + %0 = COPY $a0 %2 = ANDi %1, 15 %3 = INS killed %2, 17, 17, %0 - %v0 = COPY %3 - RetRA implicit %v0 + $v0 = COPY %3 + RetRA implicit $v0 ... diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir index a284fdb5799..eeac163a215 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir @@ -18,8 +18,8 @@ registers: - { id: 2, class: gpr32, preferred-register: '' } - { id: 3, class: gpr32, preferred-register: '' } liveins: - - { reg: '%a0', virtual-reg: '%0' } - - { reg: '%a1', virtual-reg: '%1' } + - { reg: '$a0', virtual-reg: '%0' } + - { reg: '$a1', virtual-reg: '%1' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -42,13 +42,13 @@ stack: constants: body: | bb.0.entry: - liveins: %a0, %a1 + liveins: $a0, $a1 - %1 = COPY %a1 - %0 = COPY %a0 + %1 = COPY $a1 + %0 = COPY $a0 %2 = ANDi %1, 15 %3 = INS killed %2, 32, 4, %0 - %v0 = COPY %3 - RetRA implicit %v0 + $v0 = COPY %3 + RetRA implicit $v0 ... diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir index 6cd839a01c6..6beb781df3b 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir @@ -18,8 +18,8 @@ registers: - { id: 2, class: gpr32, preferred-register: '' } - { id: 3, class: gpr32, preferred-register: '' } liveins: - - { reg: '%a0', virtual-reg: '%0' } - - { reg: '%a1', virtual-reg: '%1' } + - { reg: '$a0', virtual-reg: '%0' } + - { reg: '$a1', virtual-reg: '%1' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false @@ -42,13 +42,13 @@ stack: constants: body: | bb.0.entry: - liveins: %a0, %a1 + liveins: $a0, $a1 - %1 = COPY %a1 - %0 = COPY %a0 + %1 = COPY $a1 + %0 = COPY $a0 %2 = ANDi %1, 15 %3 = INS killed %2, 0, 40, %0 - %v0 = COPY %3 - RetRA implicit %v0 + $v0 = COPY %3 + RetRA implicit $v0 ... |
