[mips] Promote the result of SETCC nodes to GPR width.

Summary:
This patch modifies the existing comparison, branch, conditional-move
and select patterns, and adds new ones where needed. Also, the updated
SLT{u,i,iu} set of instructions generate a GPR width result.

The majority of the code changes in the Mips back-end fix the wrong
assumption that the result of SETCC nodes always produce an i32 value.
The changes in the common code path account for the fact that in 64-bit
MIPS targets, i1 is promoted to i32 instead of i64.

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D10970

llvm-svn: 262316

1 files changed, 116 insertions, 58 deletions

diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index aa1f09bf7ab..4613f698bd0 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -29,17 +29,21 @@ define i32 @oeq_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
+; FIXME: The sign extension below is redundant.
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    andi $2, $[[T1]], 1
+; 64-CMP-DAG:    dmfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    sll $[[T2:[0-9]+]], $[[T1]], 0
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
@@ -53,9 +57,11 @@ define i32 @ogt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -77,9 +83,11 @@ define i32 @oge_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -101,9 +109,11 @@ define i32 @olt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -125,9 +135,11 @@ define i32 @ole_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -149,9 +161,11 @@ define i32 @one_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -175,9 +189,11 @@ define i32 @ord_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -201,9 +217,11 @@ define i32 @ueq_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -225,9 +243,11 @@ define i32 @ugt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -249,9 +269,11 @@ define i32 @uge_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -273,9 +295,11 @@ define i32 @ult_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -298,9 +322,11 @@ define i32 @ule_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -322,9 +348,11 @@ define i32 @une_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -348,9 +376,11 @@ define i32 @uno_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -390,9 +420,11 @@ define i32 @oeq_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -414,9 +446,11 @@ define i32 @ogt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -438,9 +472,11 @@ define i32 @oge_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -462,9 +498,11 @@ define i32 @olt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -486,9 +524,11 @@ define i32 @ole_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -510,9 +550,11 @@ define i32 @one_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -536,9 +578,11 @@ define i32 @ord_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -562,9 +606,11 @@ define i32 @ueq_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -586,9 +632,11 @@ define i32 @ugt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -610,9 +658,11 @@ define i32 @uge_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -634,9 +684,11 @@ define i32 @ult_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -658,9 +710,11 @@ define i32 @ule_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -682,9 +736,11 @@ define i32 @une_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -708,9 +764,11 @@ define i32 @uno_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]