[mips] Promote the result of SETCC nodes to GPR width.

Summary:
This patch modifies the existing comparison, branch, conditional-move
and select patterns, and adds new ones where needed. Also, the updated
SLT{u,i,iu} set of instructions generate a GPR width result.

The majority of the code changes in the Mips back-end fix the wrong
assumption that the result of SETCC nodes always produce an i32 value.
The changes in the common code path account for the fact that in 64-bit
MIPS targets, i1 is promoted to i32 instead of i64.

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D10970

llvm-svn: 262316

9 files changed, 243 insertions, 177 deletions

diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll
index 031cce0b607..7cb96f9079e 100644
--- a/llvm/test/CodeGen/Mips/atomic.ll
+++ b/llvm/test/CodeGen/Mips/atomic.ll
@@ -344,7 +344,11 @@ entry:
 ; HAS-SEB-SEH:   seb     $[[R19:[0-9]+]], $[[R17]]
 
 ; ALL:           xor     $[[R20:[0-9]+]], $[[R19]], $5
-; ALL:           sltiu   $2, $[[R20]], 1
+
+; MIPS32-ANY:    sltiu   $2, $[[R20]], 1
+
+; MIPS64-ANY:    sltiu   $[[R21:[0-9]+]], $[[R20]], 1
+; MIPS64-ANY:    sll     $2, $[[R21]], 0
 }
 
 ; Check one i16 so that we cover the seh sign extend
diff --git a/llvm/test/CodeGen/Mips/blez_bgez.ll b/llvm/test/CodeGen/Mips/blez_bgez.ll
index dcda047f8d0..0aba5460555 100644
--- a/llvm/test/CodeGen/Mips/blez_bgez.ll
+++ b/llvm/test/CodeGen/Mips/blez_bgez.ll
@@ -1,10 +1,13 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
-; RUN: llc -march=mips64el < %s | FileCheck %s
+; RUN: llc -march=mipsel < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL
+; RUN: llc -march=mips64el < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=GP64
 
-; CHECK-LABEL: test_blez:
-; CHECK: blez ${{[0-9]+}}, $BB
+declare void @foo1()
 
 define void @test_blez(i32 %a) {
+; ALL-LABEL: test_blez:
+; ALL: blez ${{[0-9]+}}, $BB
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %if.then, label %if.end
@@ -17,13 +20,10 @@ if.end:
   ret void
 }
 
-declare void @foo1()
-
-; CHECK-LABEL: test_bgez:
-; CHECK: bgez ${{[0-9]+}}, $BB
-
 define void @test_bgez(i32 %a) {
 entry:
+; ALL-LABEL: test_bgez:
+; ALL: bgez ${{[0-9]+}}, $BB
   %cmp = icmp slt i32 %a, 0
   br i1 %cmp, label %if.then, label %if.end
 
@@ -34,3 +34,33 @@ if.then:
 if.end:
   ret void
 }
+
+define void @test_blez_64(i64 %a) {
+; GP64-LABEL: test_blez_64:
+; GP64: blez ${{[0-9]+}}, $BB
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+define void @test_bgez_64(i64 %a) {
+entry:
+; ALL-LABEL: test_bgez_64:
+; ALL: bgez ${{[0-9]+}}, $BB
+  %cmp = icmp slt i64 %a, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @foo1()
+  br label %if.end
+
+if.end:
+  ret void
+}
diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll
index a8008a2cb29..9a5e7753208 100644
--- a/llvm/test/CodeGen/Mips/cmov.ll
+++ b/llvm/test/CodeGen/Mips/cmov.ll
@@ -1,10 +1,17 @@
-; RUN: llc -march=mips     -mcpu=mips32                 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
-; RUN: llc -march=mips     -mcpu=mips32 -regalloc=basic < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
-; RUN: llc -march=mips     -mcpu=mips32r2               < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
-; RUN: llc -march=mips     -mcpu=mips32r6               < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
-; RUN: llc -march=mips64el -mcpu=mips4                  < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
-; RUN: llc -march=mips64el -mcpu=mips64                 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
-; RUN: llc -march=mips64el -mcpu=mips64r6               < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
+; RUN: llc -march=mips -mcpu=mips32 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
+; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
+; RUN: llc -march=mips -mcpu=mips32r2 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
+; RUN: llc -march=mips -mcpu=mips32r6 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
+; RUN: llc -march=mips64el -mcpu=mips4 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -check-prefix=64
+; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | \
+; RUN:    FileCheck %s -check-prefix=ALL -check-prefix=64-CMP -check-prefix=64
 
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
@@ -413,20 +420,9 @@ entry:
 ; 32-CMP-DAG:   or $3, $[[T1]], $[[T0]]
 ; 32-CMP-DAG:   addiu $2, $zero, 0
 
-; 64-CMOV-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMOV-DAG:  addiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG:  slti $[[R0:[0-9]+]], $4, 32767
-; 64-CMOV-DAG:  movz $[[I4]], $[[I5]], $[[R0]]
-
-; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  addiu $[[I4:[0-9]+]], $zero, 4
-; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, 32767
-; FIXME: We can do better than this by adding/subtracting the result of slti
-;        to/from one of the constants.
-; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
-
+; 64-DAG:  daddiu  $[[T0:[0-9]+]], $zero, 32766
+; 64-DAG:  slt     $[[T1:[0-9]+]], $[[T0]], $4
+; 64-DAG:  ori     $2, $[[T1]], 4
 define i64 @slti64_0(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, 32766
@@ -458,21 +454,9 @@ entry:
 ; 32-CMP-DAG:   or $3, $[[T1]], $[[T0]]
 ; 32-CMP-DAG:   addiu $2, $zero, 0
 
-; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767
-; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
-; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
-
-; 64-CMP-DAG:  daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  daddiu $[[I4:2]], $zero, 4
-; 64-CMP-DAG:  daddiu $[[R1:[0-9]+]], $zero, 32767
-; 64-CMP-DAG:  slt $[[R0:[0-9]+]], $[[R1]], $4
-; FIXME: We can do better than this by using selccz to choose between -0 and -2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
-
+; 64-DAG:  daddiu $[[T0:[0-9]+]], $zero, 32767
+; 64-DAG:  slt $[[T1:[0-9]+]], $[[T0]], $4
+; 64-DAG:  ori $2, $[[T1]], 4
 define i64 @slti64_1(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, 32767
@@ -480,27 +464,23 @@ entry:
   ret i64 %conv
 }
 
-; ALL-LABEL: slti64_2:
-
-; FIXME: The 32-bit versions of this test are too complicated to reasonably
-;        match at the moment. They do show some missing optimizations though
-;        such as:
-;           (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)
+; ALL-LABEL: slti32_2:
 
-; 64-CMOV-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
-; 64-CMOV-DAG:  addiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG:  slti $[[R0:[0-9]+]], $4, -32768
-; 64-CMOV-DAG:  movz $[[I4]], $[[I3]], $[[R0]]
+; FIXME: Remove unecessary sign-extension.
+; 64-DAG:  slti    $[[T0:[0-9]+]], $4, -32768
+; 64-DAG:  sll     $[[T1:[0-9]+]], $[[T0]], 0
+; 64-DAG:  addiu   $2, $[[T1]], 3
+define i32 @slti32_2(i32 signext %a) {
+entry:
+  %cmp = icmp sgt i32 %a, -32769
+  %conv = select i1 %cmp, i32 3, i32 4
+  ret i32 %conv
+}
 
-; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
-; 64-CMP-DAG:  addiu $[[I4:[0-9]+]], $zero, 4
-; 64-CMP-DAG:  slti $[[R0:[0-9]+]], $4, -32768
-; FIXME: We can do better than this by adding/subtracting the result of slti
-;        to/from one of the constants.
-; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I3]], $[[R0]]
-; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
+; ALL-LABEL: slti64_2:
 
+; 64-DAG:  slti    $[[T0:[0-9]+]], $4, -32768
+; 64-DAG:  daddiu  $2, $[[T0]], 3
 define i64 @slti64_2(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, -32769
@@ -508,28 +488,24 @@ entry:
   ret i64 %conv
 }
 
-; ALL-LABEL: slti64_3:
-
-; FIXME: The 32-bit versions of this test are too complicated to reasonably
-;        match at the moment. They do show some missing optimizations though
-;        such as:
-;           (movz $a, $b, (neg $c)) -> (movn $a, $b, $c)
+; ALL-LABEL: slti32_3:
 
-; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
-; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
-; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4
-; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
+; FIXME: Remove unecessary sign-extension.
+; 64-DAG: slt     $[[R0:[0-9]+]], ${{[0-9]+}}, $4
+; 64-DAG: sll     $[[R1:[0-9]+]], $[[R0]], 0
+; 64-DAG: ori     $2, $[[R1]], 4
+define i32 @slti32_3(i32 signext %a) {
+entry:
+  %cmp = icmp sgt i32 %a, -32770
+  %conv = select i1 %cmp, i32 5, i32 4
+  ret i32 %conv
+}
 
-; 64-CMP-DAG:  daddiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  daddiu $[[I4:2]], $zero, 4
-; 64-CMP-DAG:  daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766
-; 64-CMP-DAG:  slt $[[R0:[0-9]+]], $[[R1]], $4
-; FIXME: We can do better than this by using selccz to choose between -0 and -2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]]
-; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
+; ALL-LABEL: slti64_3:
 
+; 64-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32766
+; 64-DAG: slt $[[R1:[0-9]+]], $[[R0]], $4
+; 64-DAG: ori $2, $[[R1]], 4
 define i64 @slti64_3(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, -32770
diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll
index b7aad049e8a..90a459d7d4a 100644
--- a/llvm/test/CodeGen/Mips/countleading.ll
+++ b/llvm/test/CodeGen/Mips/countleading.ll
@@ -4,7 +4,7 @@
 ; RUN: llc -march=mips64el -mcpu=mips4    < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
 ; RUN: llc -march=mips64el -mcpu=mips64   < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
-; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
 
 ; Prefixes:
 ;   ALL      - All
diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index aa1f09bf7ab..4613f698bd0 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -29,17 +29,21 @@ define i32 @oeq_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; 32-CMP-DAG:    andi $2, $[[T1]], 1
 
+; FIXME: The sign extension below is redundant.
 ; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG:    andi $2, $[[T1]], 1
+; 64-CMP-DAG:    dmfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG:    sll $[[T2:[0-9]+]], $[[T1]], 0
+; 64-CMP-DAG:    andi $2, $[[T2]], 1
 
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
@@ -53,9 +57,11 @@ define i32 @ogt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -77,9 +83,11 @@ define i32 @oge_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -101,9 +109,11 @@ define i32 @olt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -125,9 +135,11 @@ define i32 @ole_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -149,9 +161,11 @@ define i32 @one_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -175,9 +189,11 @@ define i32 @ord_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -201,9 +217,11 @@ define i32 @ueq_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ueq.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -225,9 +243,11 @@ define i32 @ugt_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ole.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -249,9 +269,11 @@ define i32 @uge_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.olt.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -273,9 +295,11 @@ define i32 @ult_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ult.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -298,9 +322,11 @@ define i32 @ule_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.ule.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -322,9 +348,11 @@ define i32 @une_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.eq.s $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.s $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -348,9 +376,11 @@ define i32 @uno_f32(float %a, float %b) nounwind {
 ; 32-C-DAG:      c.un.s $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.s $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -390,9 +420,11 @@ define i32 @oeq_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -414,9 +446,11 @@ define i32 @ogt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -438,9 +472,11 @@ define i32 @oge_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -462,9 +498,11 @@ define i32 @olt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -486,9 +524,11 @@ define i32 @ole_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -510,9 +550,11 @@ define i32 @one_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -536,9 +578,11 @@ define i32 @ord_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -562,9 +606,11 @@ define i32 @ueq_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ueq.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ueq.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -586,9 +632,11 @@ define i32 @ugt_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ole.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ole.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -610,9 +658,11 @@ define i32 @uge_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.olt.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.olt.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -634,9 +684,11 @@ define i32 @ult_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ult.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ult.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -658,9 +710,11 @@ define i32 @ule_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.ule.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.ule.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -682,9 +736,11 @@ define i32 @une_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.eq.d $f12, $f14
 ; 32-C:          movt $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.eq.d $f12, $f13
-; 64-C:          movt $2, $zero, $fcc0
+; 64-C-DAG:      movt $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
@@ -708,9 +764,11 @@ define i32 @uno_f64(double %a, double %b) nounwind {
 ; 32-C-DAG:      c.un.d $f12, $f14
 ; 32-C:          movf $2, $zero, $fcc0
 
-; 64-C-DAG:      addiu $2, $zero, 1
+; FIXME: Remove redundant sign extension.
+; 64-C-DAG:      daddiu $[[T0:[0-9]+]], $zero, 1
 ; 64-C-DAG:      c.un.d $f12, $f13
-; 64-C:          movf $2, $zero, $fcc0
+; 64-C-DAG:      movf $[[T0]], $zero, $fcc0
+; 64-C:          sll $2, $[[T0]], 0
 
 ; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
 ; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
index 6067cfb3b1c..ed8d9030ccf 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
@@ -29,7 +29,7 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
-define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
+define double @tst_select_i1_double(i1 %s, double %x, double %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_double:
 
@@ -53,8 +53,10 @@ entry:
 
   ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
   ; SEL-32:     mthc1   $6, $[[F0]]
+  ; SEL-32:     sll     $[[T0:[0-9]+]], $4, 31
+  ; SEL-32:     sra     $[[T1:[0-9]+]], $[[T0]], 31
   ; SEL-32:     ldc1    $[[F1:f[0-9]+]], 16($sp)
-  ; SEL-32:     mtc1    $4, $f0
+  ; SEL-32:     mtc1    $[[T1]], $f0
   ; SEL-32:     sel.d   $f0, $[[F1]], $[[F0]]
 
   ; M3:         andi    $[[T0:[0-9]+]], $4, 1
@@ -69,14 +71,15 @@ entry:
   ; CMOV-64:    movn.d  $f14, $f13, $[[T0]]
   ; CMOV-64:    mov.d   $f0, $f14
 
-  ; SEL-64:     mtc1    $4, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $4, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.d   $f0, $f14, $f13
   %r = select i1 %s, double %x, double %y
   ret double %r
 }
 
-define double @tst_select_i1_double_reordered(double %x, double %y,
-                                              i1 signext %s) {
+define double @tst_select_i1_double_reordered(double %x, double %y, i1 %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_double_reordered:
 
@@ -110,7 +113,9 @@ entry:
   ; CMOV-64:    movn.d  $f13, $f12, $[[T0]]
   ; CMOV-64:    mov.d   $f0, $f13
 
-  ; SEL-64:     mtc1    $6, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $6, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.d   $f0, $f13, $f12
   %r = select i1 %s, double %x, double %y
   ret double %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
index 173055a5ef5..c554c6983bf 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
@@ -29,7 +29,7 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
-define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
+define float @tst_select_i1_float(i1 %s, float %x, float %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_float:
 
@@ -51,21 +51,24 @@ entry:
 
   ; SEL-32:     mtc1    $5, $[[F0:f[0-9]+]]
   ; SEL-32:     mtc1    $6, $[[F1:f[0-9]+]]
-  ; SEL-32:     mtc1    $4, $f0
+  ; SEL-32:     sll     $[[T0:[0-9]+]], $4, 31
+  ; SEL-32:     sra     $[[T1:[0-9]+]], $[[T0]], 31
+  ; SEL-32:     mtc1    $[[T1]], $f0
   ; SEL-32:     sel.s   $f0, $[[F1]], $[[F0]]
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
   ; CMOV-64:    movn.s  $f14, $f13, $[[T0]]
   ; CMOV-64:    mov.s   $f0, $f14
 
-  ; SEL-64:     mtc1    $4, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $4, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.s   $f0, $f14, $f13
   %r = select i1 %s, float %x, float %y
   ret float %r
 }
 
-define float @tst_select_i1_float_reordered(float %x, float %y,
-                                            i1 signext %s) {
+define float @tst_select_i1_float_reordered(float %x, float %y, i1 %s) {
 entry:
   ; ALL-LABEL: tst_select_i1_float_reordered:
 
@@ -82,14 +85,18 @@ entry:
   ; CMOV-32:    movn.s  $f14, $f12, $[[T0]]
   ; CMOV-32:    mov.s   $f0, $f14
 
-  ; SEL-32:     mtc1    $6, $f0
+  ; SEL-32:     sll     $[[T0:[0-9]+]], $6, 31
+  ; SEL-32:     sra     $[[T1:[0-9]+]], $[[T0]], 31
+  ; SEL-32:     mtc1    $[[T1]], $f0
   ; SEL-32:     sel.s   $f0, $f14, $f12
 
   ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
   ; CMOV-64:    movn.s  $f13, $f12, $[[T0]]
   ; CMOV-64:    mov.s   $f0, $f13
 
-  ; SEL-64:     mtc1    $6, $f0
+  ; SEL-64:     dsll    $[[T0:[0-9]+]], $6, 63
+  ; SEL-64:     dsra    $[[T1:[0-9]+]], $[[T0]], 63
+  ; SEL-64:     dmtc1   $[[T1]], $f0
   ; SEL-64:     sel.s   $f0, $f13, $f12
   %r = select i1 %s, float %x, float %y
   ret float %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
index 87f2ca4b8a1..c4632fb3c8e 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -29,8 +29,7 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
 
-define signext i1 @tst_select_i1_i1(i1 signext %s,
-                                    i1 signext %x, i1 signext %y) {
+define signext i1 @tst_select_i1_i1(i1 %s, i1 signext %x, i1 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i1:
 
@@ -54,8 +53,7 @@ entry:
   ret i1 %r
 }
 
-define signext i8 @tst_select_i1_i8(i1 signext %s,
-                                    i8 signext %x, i8 signext %y) {
+define signext i8 @tst_select_i1_i8(i1 %s, i8 signext %x, i8 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i8:
 
@@ -79,8 +77,7 @@ entry:
   ret i8 %r
 }
 
-define signext i32 @tst_select_i1_i32(i1 signext %s,
-                                      i32 signext %x, i32 signext %y) {
+define signext i32 @tst_select_i1_i32(i1 %s, i32 signext %x, i32 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i32:
 
@@ -104,8 +101,7 @@ entry:
   ret i32 %r
 }
 
-define signext i64 @tst_select_i1_i64(i1 signext %s,
-                                      i64 signext %x, i64 signext %y) {
+define signext i64 @tst_select_i1_i64(i1 %s, i64 signext %x, i64 signext %y) {
 entry:
   ; ALL-LABEL: tst_select_i1_i64:
 
@@ -152,8 +148,6 @@ entry:
   ; CMOV-64:    move    $2, $6
 
   ; SEL-64:     andi    $[[T0:[0-9]+]], $4, 1
-  ; FIXME: This shift is redundant
-  ; SEL-64:     sll     $[[T0]], $[[T0]], 0
   ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
   ; SEL-64:     or      $2, $[[T0]], $[[T1]]
diff --git a/llvm/test/CodeGen/Mips/octeon.ll b/llvm/test/CodeGen/Mips/octeon.ll
index 499ce3c1ddb..2b413d7a55b 100644
--- a/llvm/test/CodeGen/Mips/octeon.ll
+++ b/llvm/test/CodeGen/Mips/octeon.ll
@@ -32,10 +32,8 @@ entry:
 ; OCTEON: jr     $ra
 ; OCTEON: seq    $2, $4, $5
 ; MIPS64: xor    $[[T0:[0-9]+]], $4, $5
-; MIPS64: sltiu  $[[T1:[0-9]+]], $[[T0]], 1
-; MIPS64: dsll   $[[T2:[0-9]+]], $[[T1]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T2]], 32
+; MIPS64: sltiu  $2, $[[T0]], 1
   %res = icmp eq i64 %a, %b
   %res2 = zext i1 %res to i64
   ret i64 %res2
@@ -48,10 +46,8 @@ entry:
 ; OCTEON: seqi   $2, $4, 42
 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
 ; MIPS64: xor    $[[T1:[0-9]+]], $4, $[[T0]]
-; MIPS64: sltiu  $[[T2:[0-9]+]], $[[T1]], 1
-; MIPS64: dsll   $[[T3:[0-9]+]], $[[T2]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T3]], 32
+; MIPS64: sltiu  $2, $[[T1]], 1
   %res = icmp eq i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2
@@ -63,10 +59,8 @@ entry:
 ; OCTEON: jr     $ra
 ; OCTEON: sne    $2, $4, $5
 ; MIPS64: xor    $[[T0:[0-9]+]], $4, $5
-; MIPS64: sltu   $[[T1:[0-9]+]], $zero, $[[T0]]
-; MIPS64: dsll   $[[T2:[0-9]+]], $[[T1]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T2]], 32
+; MIPS64: sltu   $2, $zero, $[[T0]]
   %res = icmp ne i64 %a, %b
   %res2 = zext i1 %res to i64
   ret i64 %res2
@@ -79,10 +73,8 @@ entry:
 ; OCTEON: snei   $2, $4, 42
 ; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
 ; MIPS64: xor    $[[T1:[0-9]+]], $4, $[[T0]]
-; MIPS64: sltu   $[[T2:[0-9]+]], $zero, $[[T1]]
-; MIPS64: dsll   $[[T3:[0-9]+]], $[[T2]], 32
 ; MIPS64: jr     $ra
-; MIPS64: dsrl   $2, $[[T3]], 32
+; MIPS64: sltu   $2, $zero, $[[T1]]
   %res = icmp ne i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2