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| author | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-06-16 07:06:25 +0000 |
|---|---|---|
| committer | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-06-16 07:06:25 +0000 |
| commit | f1e0a03d0827d34cbf51bed9faeb4c17095217cc (patch) | |
| tree | 92d991b7bce6a136596c0b4fab757559de3184e3 /llvm/test/CodeGen/Mips/countleading.ll | |
| parent | a4cfb620dfe6a694fcb578d84ca252f0da473388 (diff) | |
| download | bcm5719-llvm-f1e0a03d0827d34cbf51bed9faeb4c17095217cc.tar.gz bcm5719-llvm-f1e0a03d0827d34cbf51bed9faeb4c17095217cc.zip | |
[mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructions
Differential Revision: http://reviews.llvm.org/D16917
llvm-svn: 272876
Diffstat (limited to 'llvm/test/CodeGen/Mips/countleading.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/countleading.ll | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll index b7aad049e8a..16a7b067e11 100644 --- a/llvm/test/CodeGen/Mips/countleading.ll +++ b/llvm/test/CodeGen/Mips/countleading.ll @@ -4,7 +4,8 @@ ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s -; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefix=ALL -check-prefix=MICROMIPS64 %s ; Prefixes: ; ALL - All @@ -21,6 +22,8 @@ entry: ; MIPS64-GT-R1: clz $2, $4 +; MICROMIPS64: clz $2, $4 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) ret i32 %tmp1 } @@ -37,6 +40,8 @@ entry: ; MIPS64-GT-R1: clo $2, $4 +; MICROMIPS64: clo $2, $4 + %neg = xor i32 %X, -1 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) ret i32 %tmp1 @@ -58,6 +63,7 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclz $2, $4 +; MICROMIPS64: dclz $2, $4 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) ret i64 %tmp1 @@ -83,6 +89,7 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclo $2, $4 +; MICROMIPS64: dclo $2, $4 %neg = xor i64 %X, -1 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) |
