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| author | Tim Northover <tnorthover@apple.com> | 2014-03-11 10:48:52 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-03-11 10:48:52 +0000 |
| commit | e94a518a22db4b21f4a4a9e34173a11e9dfc5fcc (patch) | |
| tree | 054bf7c2cdd888931fdabadb91d82dbb78b05f2b /llvm/test/CodeGen/Mips/atomicops.ll | |
| parent | aab3cfe023752c32da984afb281d322d631ad298 (diff) | |
| download | bcm5719-llvm-e94a518a22db4b21f4a4a9e34173a11e9dfc5fcc.tar.gz bcm5719-llvm-e94a518a22db4b21f4a4a9e34173a11e9dfc5fcc.zip | |
IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:
cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic
where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).
rdar://problem/15996804
llvm-svn: 203559
Diffstat (limited to 'llvm/test/CodeGen/Mips/atomicops.ll')
| -rw-r--r-- | llvm/test/CodeGen/Mips/atomicops.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/atomicops.ll b/llvm/test/CodeGen/Mips/atomicops.ll index 0f0f01afc14..dc07c637418 100644 --- a/llvm/test/CodeGen/Mips/atomicops.ll +++ b/llvm/test/CodeGen/Mips/atomicops.ll @@ -20,7 +20,7 @@ entry: %add.i = add nsw i32 %0, 2 %1 = load volatile i32* %x, align 4 %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %add.i, i32 %1) nounwind - %2 = cmpxchg i32* %x, i32 1, i32 2 seq_cst + %2 = cmpxchg i32* %x, i32 1, i32 2 seq_cst seq_cst %3 = load volatile i32* %x, align 4 %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3) nounwind %4 = atomicrmw xchg i32* %x, i32 1 seq_cst |
