MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.

Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.

Differential Revision: http://reviews.llvm.org/D22722

llvm-svn: 279600

37 files changed, 2 insertions, 53 deletions

diff --git a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
index 3427dfa371a..adf711a8c67 100644
--- a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir
@@ -10,7 +10,6 @@
 
 ---
 name:            baz
-isSSA:           true
 registers:
   - { id: 0, class: _ }
 body: |
diff --git a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
index c8fc49c07e1..f80f4ee0cdb 100644
--- a/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir
@@ -11,7 +11,6 @@
 
 ---
 name:            bar
-isSSA:           true
 registers:
   - { id: 0, class: gpr }
 body: |
diff --git a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
index 2d966ece768..a0749980241 100644
--- a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
@@ -35,7 +35,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: false
 tracksSubRegLiveness: false
 liveins:
diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir b/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir
index 9ea5c6811b6..e7e0dda53c5 100644
--- a/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir
@@ -22,7 +22,6 @@
 # CHECK: LDRWui %x0, 1
 # CHECK: STRWui %w1, %x0, 2
 name:            load_imp-def
-isSSA:           true
 body:             |
   bb.0.entry:
     liveins: %w1, %x0
diff --git a/llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir b/llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
index a2ad2092cb0..fc0c4ce8c07 100644
--- a/llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
@@ -15,7 +15,6 @@
 ...
 ---
 name:            stack_local
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr64common }
diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
index fef447f1708..21b64c1ecd5 100644
--- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
+++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
@@ -92,7 +92,6 @@ alignment:       1
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: true
-isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:
diff --git a/llvm/test/CodeGen/MIR/Generic/frame-info.mir b/llvm/test/CodeGen/MIR/Generic/frame-info.mir
index 71448c8a71b..7c6e6ebbfee 100644
--- a/llvm/test/CodeGen/MIR/Generic/frame-info.mir
+++ b/llvm/test/CodeGen/MIR/Generic/frame-info.mir
@@ -23,7 +23,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 
 # CHECK: frameInfo:
@@ -49,7 +48,6 @@ body: |
 ...
 ---
 name:            test2
-isSSA:           true
 tracksRegLiveness: true
 
 # CHECK: test2
diff --git a/llvm/test/CodeGen/MIR/Generic/register-info.mir b/llvm/test/CodeGen/MIR/Generic/register-info.mir
index bf90196b3e6..97a6593f364 100644
--- a/llvm/test/CodeGen/MIR/Generic/register-info.mir
+++ b/llvm/test/CodeGen/MIR/Generic/register-info.mir
@@ -17,8 +17,7 @@
 ...
 ---
 # CHECK: name: foo
-# CHECK:      isSSA: false
-# CHECK-NEXT: tracksRegLiveness: false
+# CHECK: tracksRegLiveness: false
 # CHECK-NEXT: tracksSubRegLiveness: false
 # CHECK: ...
 name:            foo
@@ -27,12 +26,10 @@ body: |
 ...
 ---
 # CHECK: name: bar
-# CHECK:      isSSA: false
-# CHECK-NEXT: tracksRegLiveness: true
+# CHECK: tracksRegLiveness: true
 # CHECK-NEXT: tracksSubRegLiveness: true
 # CHECK: ...
 name: bar
-isSSA: false
 tracksRegLiveness: true
 tracksSubRegLiveness: true
 body: |
diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir
index 763fe2b9b96..1f2ebe52f13 100644
--- a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir
+++ b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir
@@ -177,7 +177,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -225,7 +224,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -271,7 +269,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -321,7 +318,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -371,7 +367,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -421,7 +416,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -471,7 +465,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -521,7 +514,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
@@ -635,7 +627,6 @@ alignment:       2
 exposesReturnsTwice: false
 hasInlineAsm:    false
 allVRegsAllocated: false
-isSSA:           true
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 registers:       
diff --git a/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir b/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
index 3caab2c7a57..d1c38acd5d3 100644
--- a/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
+++ b/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
@@ -20,7 +20,6 @@
 ...
 ---
 name:            main
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: g8rc_and_g8rc_nox0 }
diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
index c5d7d5eb289..d2729978669 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
@@ -39,7 +39,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
index c94fd9f5028..3f668cd815f 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
@@ -39,7 +39,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
index a6384bb0719..af563bd672a 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
index 5796c18eced..e9c49c02348 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
index cdfcabbbf82..e5b0183c44d 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/function-liveins.mir b/llvm/test/CodeGen/MIR/X86/function-liveins.mir
index cbdc36281b7..a388bfac3b0 100644
--- a/llvm/test/CodeGen/MIR/X86/function-liveins.mir
+++ b/llvm/test/CodeGen/MIR/X86/function-liveins.mir
@@ -13,7 +13,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
index 8545acc2263..aad0a77261e 100644
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -18,7 +18,6 @@
 
 ---
 name:            test_vregs
-isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: _ }
 # CHECK-NEXT:   - { id: 1, class: _ }
@@ -50,7 +49,6 @@ body: |
 
 ---
 name:            test_unsized
-isSSA:           true
 body: |
   bb.0:
     successors: %bb.0
diff --git a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
index 12ee5d873d9..aa6cd5a0a45 100644
--- a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
+++ b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
@@ -50,7 +50,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
@@ -72,7 +71,6 @@ body: |
 ...
 ---
 name:            test_typed_immediates
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir b/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
index 42d05274e7c..c921e497d46 100644
--- a/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
@@ -34,7 +34,6 @@
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
diff --git a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir
index 42f3fe1c86c..9d92fe5c2c6 100644
--- a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir
@@ -41,7 +41,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
index d80b7d0bfcb..a893b0836a6 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
@@ -46,7 +46,6 @@
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
index 2115a11ae69..12f731e2f55 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
@@ -15,7 +15,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir b/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
index 6ff15aef4d7..1c5208ee30e 100644
--- a/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
@@ -17,7 +17,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
index b5039339028..c840dd52de1 100644
--- a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir
@@ -7,7 +7,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
index a9a45adadf6..e6c7c6e2e4c 100644
--- a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
@@ -16,7 +16,6 @@
 # CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
 # CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir
index a69fe087b0d..6dd44aec07a 100644
--- a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
index 18cb758408f..35879b7036d 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
@@ -14,7 +14,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir b/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
index 70b413b5ad3..f17fc7e8ef9 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   # CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200'
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
index 5d40791b4c3..cbf0322860e 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
index fe41e0a4d2f..123d9b98167 100644
--- a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
index 7f156120c5e..9e156e72064 100644
--- a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
+++ b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir
@@ -4,7 +4,6 @@
 
 ---
 name:            test_size_physreg
-isSSA:           true
 registers:
 body: |
   bb.0.entry:
diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
index b9b7a307347..b54a8da3b21 100644
--- a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
+++ b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
@@ -4,7 +4,6 @@
 
 ---
 name:            test_size_regclass
-isSSA:           true
 registers:
   - { id: 0, class: gr32 }
 body: |
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
index 793f9123776..3c709eb9423 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
@@ -39,7 +39,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
index 2d997b07dbd..1f4f9c63157 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
index 2751bc25174..090ca52930a 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir
@@ -12,7 +12,6 @@
 ...
 ---
 name:            t
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
index 4d2350a01b8..6ecfabc1b30 100644
--- a/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir
@@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-isSSA:           true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
index 3f7b0fdcc0e..e63bcf4acdd 100644
--- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -31,7 +31,6 @@
 ...
 ---
 name:            bar
-isSSA:           true
 tracksRegLiveness: true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gr32 }
@@ -65,7 +64,6 @@ body: |
 ...
 ---
 name:            foo
-isSSA:           true
 tracksRegLiveness: true
 # CHECK: name: foo
 # CHECK:      registers: