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| author | Jun Bum Lim <junbuml@codeaurora.org> | 2016-03-31 20:53:47 +0000 |
|---|---|---|
| committer | Jun Bum Lim <junbuml@codeaurora.org> | 2016-03-31 20:53:47 +0000 |
| commit | 760afcb3383a016de966700b5eb837f153cabd7b (patch) | |
| tree | feb08f5c9f055e01d502e4139537a55a0662f970 /llvm/test/CodeGen/MIR | |
| parent | 9defda528e54bd6d34f2f26b6a7822523072f3cf (diff) | |
| download | bcm5719-llvm-760afcb3383a016de966700b5eb837f153cabd7b.tar.gz bcm5719-llvm-760afcb3383a016de966700b5eb837f153cabd7b.zip | |
[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()
Summary:
This change will allow loads with imp-def to be clustered in machine-scheduler pass.
areMemAccessesTriviallyDisjoint() can also handle loads with imp-def.
Reviewers: mcrosier, jmolloy, t.p.northover
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D18665
llvm-svn: 265051
Diffstat (limited to 'llvm/test/CodeGen/MIR')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir b/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir new file mode 100644 index 00000000000..a6de39a1dae --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/machine-scheduler.mir @@ -0,0 +1,35 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s + +--- | + define i64 @load_imp-def(i64* nocapture %P, i32 %v) { + entry: + %0 = bitcast i64* %P to i32* + %1 = load i32, i32* %0 + %conv = zext i32 %1 to i64 + %arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1 + %arrayidx1 = bitcast i64* %arrayidx19 to i32* + store i32 %v, i32* %arrayidx1 + %2 = load i64, i64* %arrayidx19 + %and = and i64 %2, 4294967295 + %add = add nuw nsw i64 %and, %conv + ret i64 %add + } +... +--- +# CHECK-LABEL: name: load_imp-def +# CHECK: bb.0.entry: +# CHECK: LDRWui %x0, 0 +# CHECK: LDRWui %x0, 1 +# CHECK: STRWui %w1, %x0, 2 +name: load_imp-def +isSSA: true +body: | + bb.0.entry: + liveins: %w1, %x0 + %w8 = LDRWui %x0, 1, implicit-def %x8 :: (load 4 from %ir.0) + STRWui killed %w1, %x0, 2 :: (store 4 into %ir.arrayidx1) + %w9 = LDRWui killed %x0, 0, implicit-def %x9 :: (load 4 from %ir.arrayidx19, align 8) + %x0 = ADDXrr killed %x9, killed %x8 + RET_ReallyLR implicit %x0 +... + |
