MIR Parser: Verify the implicit machine register operands.

This commit verifies that the parsed machine instructions contain the implicit
register operands as specified by the MCInstrDesc. Variadic and call
instructions aren't verified.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10781

llvm-svn: 241537

12 files changed, 142 insertions, 26 deletions

diff --git a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
new file mode 100644
index 00000000000..c5f5aaca34e
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
@@ -0,0 +1,38 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+
+...
+---
+name:            foo
+body:
+ - id:              0
+   name:            entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
+# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
+     - 'JG_1 %bb.2.exit, implicit %eax'
+ - id:              1
+   name:            less
+   instructions:
+     - '%eax = MOV32r0 implicit-def %eflags'
+ - id:              2
+   name:            exit
+   instructions:
+     - 'RETQ %eax'
+...
diff --git a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
new file mode 100644
index 00000000000..ecf3a122bf6
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
@@ -0,0 +1,38 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+
+...
+---
+name:            foo
+body:
+ - id:              0
+   name:            entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
+# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
+     - 'JG_1 %bb.2.exit, implicit-def %eflags'
+ - id:              1
+   name:            less
+   instructions:
+     - '%eax = MOV32r0 implicit-def %eflags'
+ - id:              2
+   name:            exit
+   instructions:
+     - 'RETQ %eax'
+...
diff --git a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
index f4248a76be4..5343a847fbb 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
@@ -23,13 +23,13 @@ body:
    name:   entry
    instructions:
      - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
      # CHECK: [[@LINE+1]]:18: expected a number after '%bb.'
-     - 'JG_1 %bb.nah'
+     - 'JG_1 %bb.nah, implicit %eflags'
  - id: 1
    name: yes
    instructions:
-     - '%eax = MOV32r0'
+     - '%eax = MOV32r0 implicit-def %eflags'
  - id: 2
    name: nah
    instructions:
diff --git a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir
index 4aa88fe96ce..3ea729b0055 100644
--- a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir
@@ -31,7 +31,7 @@ body:
       # CHECK: - '%rax = MOV64rm %rip, 1, _, @G, _'
       - '%rax = MOV64rm %rip, 1, _, @G, _'
       - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax'
+      - '%eax = INC32r %eax, implicit-def %eflags'
       - 'RETQ %eax'
 ...
 ---
@@ -44,6 +44,6 @@ body:
       # CHECK: - '%rax = MOV64rm %rip, 1, _, @0, _'
       - '%rax = MOV64rm %rip, 1, _, @0, _'
       - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax'
+      - '%eax = INC32r %eax, implicit-def %eflags'
       - 'RETQ %eax'
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
index 61a5bdfe2ed..fdb25c907f5 100644
--- a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
@@ -23,12 +23,12 @@ body:
    name: entry
    instructions:
      - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
      # CHECK: [[@LINE+1]]:14: expected 32-bit integer (too large)
-     - 'JG_1 %bb.123456789123456'
+     - 'JG_1 %bb.123456789123456, implicit %eflags'
  - id: 1
    instructions:
-     - '%eax = MOV32r0'
+     - '%eax = MOV32r0 implicit-def %eflags'
  - id: 2
    instructions:
      - 'RETQ %eax'
diff --git a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
index 9d1bd0bd58a..607acb5f273 100644
--- a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
@@ -41,13 +41,13 @@ body:
      - '%eax = MOV32rm %rdi, 1, _, 0, _'
      # CHECK:      - 'CMP32ri8 %eax, 10
      # CHECK-NEXT: - 'JG_1 %bb.2.exit
-     - 'CMP32ri8 %eax, 10'
-     - 'JG_1 %bb.2.exit'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
+     - 'JG_1 %bb.2.exit, implicit %eflags'
  # CHECK: name: less
  - id:              1
    name:            less
    instructions:
-     - '%eax = MOV32r0'
+     - '%eax = MOV32r0 implicit-def %eflags'
  - id:              2
    name:            exit
    instructions:
@@ -64,11 +64,11 @@ body:
      - '%eax = MOV32rm %rdi, 1, _, 0, _'
      # CHECK:      - 'CMP32ri8 %eax, 10
      # CHECK-NEXT: - 'JG_1 %bb.2
-     - 'CMP32ri8 %eax, 10'
-     - 'JG_1 %bb.3'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
+     - 'JG_1 %bb.3, implicit %eflags'
  - id: 1
    instructions:
-     - '%eax = MOV32r0'
+     - '%eax = MOV32r0 implicit-def %eflags'
  - id: 3
    instructions:
      - 'RETQ %eax'
diff --git a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir
index b743198cf27..08f3d76486b 100644
--- a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir
+++ b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir
@@ -18,8 +18,8 @@ body:
  - id:           0
    name:         entry
    instructions:
-     # CHECK:      - IMUL32rri8
+     # CHECK:      - MOV32rr
      # CHECK-NEXT: - RETQ
-     - IMUL32rri8
+     - MOV32rr
      - ' RETQ '
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
new file mode 100644
index 00000000000..4d2cd03f4a3
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
@@ -0,0 +1,40 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that the MIR parser reports an error when an instruction
+# is missing one of its implicit register operands.
+
+--- |
+
+  define i32 @foo(i32* %p) {
+  entry:
+    %a = load i32, i32* %p
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+
+...
+---
+name:            foo
+body:
+ - id:              0
+   name:            entry
+   instructions:
+     - '%eax = MOV32rm %rdi, 1, _, 0, _'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
+# CHECK: [[@LINE+1]]:24: missing implicit register operand 'implicit %eflags'
+     - 'JG_1 %bb.2.exit'
+ - id:              1
+   name:            less
+   instructions:
+     - '%eax = MOV32r0 implicit-def %eflags'
+ - id:              2
+   name:            exit
+   instructions:
+     - 'RETQ %eax'
+...
diff --git a/llvm/test/CodeGen/MIR/X86/named-registers.mir b/llvm/test/CodeGen/MIR/X86/named-registers.mir
index 5defb8489e1..91ed4856867 100644
--- a/llvm/test/CodeGen/MIR/X86/named-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/named-registers.mir
@@ -18,6 +18,6 @@ body:
    instructions:
      # CHECK:      - '%eax = MOV32r0
      # CHECK-NEXT: - 'RETQ %eax
-     - '%eax = MOV32r0'
+     - '%eax = MOV32r0 implicit-def %eflags'
      - 'RETQ %eax'
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
index 719bd9c905d..f4136598ff5 100644
--- a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir
@@ -24,7 +24,7 @@ body:
   - id:          0
     name:        body
     instructions:
-      - '%eax = IMUL32rri8 %edi, 11'
+      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
       - 'RETQ %eax'
 ...
 ---
@@ -36,8 +36,8 @@ body:
     instructions:
       # CHECK:      - 'PUSH64r %rax
       # CHECK-NEXT: - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - 'PUSH64r %rax'
+      - 'PUSH64r %rax, implicit-def %rsp, implicit %rsp'
       - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r'
+      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
       - 'RETQ %eax'
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
index 5bc979a83ea..a82e9a780f5 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
@@ -26,12 +26,12 @@ body:
    name:         entry
    instructions:
      - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
      # CHECK: [[@LINE+1]]:14: use of undefined machine basic block #4
-     - 'JG_1 %bb.4'
+     - 'JG_1 %bb.4, implicit %eflags'
  - id: 1
    instructions:
-     - '%eax = MOV32r0'
+     - '%eax = MOV32r0 implicit-def %eflags'
  - id: 2
    instructions:
      - 'RETQ %eax'
diff --git a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
index cd8c5402256..f304113f40b 100644
--- a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
+++ b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
@@ -25,13 +25,13 @@ body:
    name:            entry
    instructions:
      - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10'
+     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
      # CHECK: [[@LINE+1]]:14: the name of machine basic block #2 isn't 'hit'
-     - 'JG_1 %bb.2.hit'
+     - 'JG_1 %bb.2.hit, implicit %eflags'
  - id:              1
    name:            less
    instructions:
-     - '%eax = MOV32r0'
+     - '%eax = MOV32r0 implicit-def %eflags'
  - id:              2
    name:            exit
    instructions: