[GlobalISel] Mark newly-created gvregs as having a bank.

Also verify that we never try to set the size of a vreg associated
to a register class.

Report an error when we encounter that in MIR. Fix a testcase that
hit that error and had a size for no reason.

llvm-svn: 276012

2 files changed, 28 insertions, 2 deletions

diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
index 1f196919afa..7e5cf47008f 100644
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
@@ -10,6 +10,6 @@ registers:
 body: |
   bb.0.entry:
     liveins: %edi
-    ; CHECK: [[@LINE+1]]:20: expected a sized type
-    %0(32) = G_ADD %opaque %edi, %edi
+    ; CHECK: [[@LINE+1]]:16: expected a sized type
+    %0 = G_ADD %opaque %edi, %edi
 ...
diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
new file mode 100644
index 00000000000..981fa2179d4
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir
@@ -0,0 +1,26 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when a register operand is sized
+# but isn't generic.
+
+---
+name:            test_size_regclass
+isSSA:           true
+registers:
+  - { id: 0, class: gr32 }
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: [[@LINE+1]]:8: unexpected size on non-generic virtual register
+    %0(32) = G_ADD i32 %edi, %edi
+...
+
+---
+name:            test_size_physreg
+isSSA:           true
+registers:
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: [[@LINE+1]]:10: unexpected size on physical register
+    %edi(32) = G_ADD i32 %edi, %edi
+...