[Hexagon] Add instruction definitions for Hexagon V66

llvm-svn: 348411

5 files changed, 73 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Hexagon/dfp.ll b/llvm/test/CodeGen/Hexagon/dfp.ll
new file mode 100644
index 00000000000..e4fe10bad0b
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/dfp.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: df_add:
+; CHECK: dfadd
+define double @df_add(double %x, double %y) local_unnamed_addr #0 {
+entry:
+  %add = fadd double %x, %y
+  ret double %add
+}
+
+; CHECK-LABEL: df_sub:
+; CHECK: dfsub
+define double @df_sub(double %x, double %y) local_unnamed_addr #0 {
+entry:
+  %sub = fsub double %x, %y
+  ret double %sub
+}
+
+attributes #0 = { norecurse nounwind readnone "target-cpu"="hexagonv66" }
diff --git a/llvm/test/CodeGen/Hexagon/mnaci_v66.ll b/llvm/test/CodeGen/Hexagon/mnaci_v66.ll
new file mode 100644
index 00000000000..63f3788fe56
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/mnaci_v66.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; This test validates the generation of v66 only instruction M2_mnaci
+; CHECK: r{{[0-9]+}} -= mpyi(r{{[0-9]+}},r{{[0-9]+}})
+
+target triple = "hexagon-unknown--elf"
+
+; Function Attrs: norecurse nounwind readnone
+define i32 @_Z4testiii(i32 %a, i32 %b, i32 %c) #0 {
+entry:
+  %mul = mul nsw i32 %c, %b
+  %sub = sub nsw i32 %a, %mul
+  ret i32 %sub
+}
+
+attributes #0 = { norecurse nounwind readnone "target-cpu"="hexagonv66" "target-features"="-hvx,-long-calls" }
diff --git a/llvm/test/MC/Hexagon/quad_regs.s b/llvm/test/MC/Hexagon/quad_regs.s
new file mode 100644
index 00000000000..6805f3bdb35
--- /dev/null
+++ b/llvm/test/MC/Hexagon/quad_regs.s
@@ -0,0 +1,5 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck %s
+
+# Test for quad register parsing and printing
+# CHECK: { v3:0.w = vrmpyz(v0.b,r0.b) }
+v3:0.w = vrmpyz(v0.b,r0.b)
diff --git a/llvm/test/MC/Hexagon/v66.s b/llvm/test/MC/Hexagon/v66.s
new file mode 100644
index 00000000000..465345fb35e
--- /dev/null
+++ b/llvm/test/MC/Hexagon/v66.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck %s
+
+# CHECK: 1d8362e4 { v4.w = vsatdw(v2.w,v3.w)
+{
+  v4.w = vsatdw(v2.w, v3.w)
+  vmem(r16+#0) = v4.new
+}
+
+# CHECK: 1aaae5e0 { v1:0.w = vasrinto(v5.w,v10.w) }
+  v1:0.w = vasrinto(v5.w, v10.w)
+
+# CHECK: 1aaae5e0 { v1:0.w = vasrinto(v5.w,v10.w) }
+  v1:0 = vasrinto(v5, v10)
+
+# CHECK: 1d89ef14 { v20.w = vadd(v15.w,v9.w,q0):carry:sat }
+  v20.w = vadd(v15.w, v9.w, q0):carry:sat
+
diff --git a/llvm/test/MC/Hexagon/z-instructions.s b/llvm/test/MC/Hexagon/z-instructions.s
new file mode 100644
index 00000000000..2a2482e17d9
--- /dev/null
+++ b/llvm/test/MC/Hexagon/z-instructions.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv66 -mhvx -filetype=obj %s | llvm-objdump -mcpu=hexagonv66 -mhvx -d - | FileCheck --implicit-check-not='{' %s
+
+# CHECK:      2d00c000 { z = vmem(r0++#0) }
+z = vmem(r0++#0)
+
+# CHECK-NEXT: 2c00c000 { z = vmem(r0+#0) }
+z = vmem(r0+#0)
+
+# CHECK-NEXT: 2d00c001 { z = vmem(r0++m0) }
+z = vmem(r0++m0)
+
+# CHECK-NEXT: { v3:0.w += vrmpyz(v13.b,r3.b++)
+# CHECK-NEXT:   v13.tmp = vmem(r2++#1)
+# CHECK-NEXT:   z = vmem(r3+#0) }
+{ v13.tmp = vmem(r2++#1)
+  v3:0.w += vrmpyz(v13.b,r3.b++)
+  z = vmem(r3+#0) }