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| author | Guillaume Chatelet <gchatelet@google.com> | 2019-09-11 11:16:48 +0000 |
|---|---|---|
| committer | Guillaume Chatelet <gchatelet@google.com> | 2019-09-11 11:16:48 +0000 |
| commit | 48904e9452de81375bd55d830d08e51cc8f2ec7e (patch) | |
| tree | 870ff19fbb173ec430372a5abbf06d4b27bc3836 /llvm/test/CodeGen/Hexagon | |
| parent | d811d9115b0b2d004a568e8ebdb37ba0ea6397d1 (diff) | |
| download | bcm5719-llvm-48904e9452de81375bd55d830d08e51cc8f2ec7e.tar.gz bcm5719-llvm-48904e9452de81375bd55d830d08e51cc8f2ec7e.zip | |
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67433
llvm-svn: 371608
Diffstat (limited to 'llvm/test/CodeGen/Hexagon')
6 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/Hexagon/bank-conflict.mir b/llvm/test/CodeGen/Hexagon/bank-conflict.mir index fbef6410fa3..ee055f9ac71 100644 --- a/llvm/test/CodeGen/Hexagon/bank-conflict.mir +++ b/llvm/test/CodeGen/Hexagon/bank-conflict.mir @@ -89,7 +89,7 @@ ... --- name: f0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: liveins: diff --git a/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir b/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir index bbb2dce009c..1dd6d36435c 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir @@ -40,7 +40,7 @@ ... --- name: f0 -alignment: 4 +alignment: 16 registers: - { id: 0, class: intregs, preferred-register: '' } - { id: 1, class: intregs, preferred-register: '' } diff --git a/llvm/test/CodeGen/Hexagon/early-if-predicator.mir b/llvm/test/CodeGen/Hexagon/early-if-predicator.mir index e93a49a8ed8..785fcd9d873 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-predicator.mir +++ b/llvm/test/CodeGen/Hexagon/early-if-predicator.mir @@ -21,7 +21,7 @@ ... --- name: if-cvt -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir b/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir index 81febed7430..0db49f36731 100644 --- a/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir +++ b/llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir @@ -20,7 +20,7 @@ --- name: foo -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r0' } diff --git a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir index a5d8c09a6b5..5b953f13b1b 100644 --- a/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir +++ b/llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir @@ -56,7 +56,7 @@ ... --- name: f0 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir index b6522029270..06f3b3a7069 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir @@ -64,7 +64,7 @@ ... --- name: main -alignment: 2 +alignment: 4 tracksRegLiveness: true registers: - { id: 0, class: intregs } |
