[Hexagon] Remove support for V4

llvm-svn: 344791

1 files changed, 29 insertions, 27 deletions

diff --git a/llvm/test/CodeGen/Hexagon/validate-offset.ll b/llvm/test/CodeGen/Hexagon/validate-offset.ll
index 8de006c80b1..ed98f281e4b 100644
--- a/llvm/test/CodeGen/Hexagon/validate-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/validate-offset.ll
@@ -1,36 +1,38 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s -O0
+; RUN: llc -march=hexagon -O0 < %s
 
 ; This is a regression test which makes sure that the offset check
 ; is available for STRiw_indexed instruction. This is required
 ; by 'Hexagon Expand Predicate Spill Code' pass.
 
-define i32 @f(i32 %a, i32 %b) nounwind {
-entry:
-  %retval = alloca i32, align 4
-  %a.addr = alloca i32, align 4
-  %b.addr = alloca i32, align 4
-  store i32 %a, i32* %a.addr, align 4
-  store i32 %b, i32* %b.addr, align 4
-  %0 = load i32, i32* %a.addr, align 4
-  %1 = load i32, i32* %b.addr, align 4
-  %cmp = icmp sgt i32 %0, %1
-  br i1 %cmp, label %if.then, label %if.else
+define i32 @f0(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = alloca i32, align 4
+  %v1 = alloca i32, align 4
+  %v2 = alloca i32, align 4
+  store i32 %a0, i32* %v1, align 4
+  store i32 %a1, i32* %v2, align 4
+  %v3 = load i32, i32* %v1, align 4
+  %v4 = load i32, i32* %v2, align 4
+  %v5 = icmp sgt i32 %v3, %v4
+  br i1 %v5, label %b1, label %b2
 
-if.then:
-  %2 = load i32, i32* %a.addr, align 4
-  %3 = load i32, i32* %b.addr, align 4
-  %add = add nsw i32 %2, %3
-  store i32 %add, i32* %retval
-  br label %return
+b1:                                               ; preds = %b0
+  %v6 = load i32, i32* %v1, align 4
+  %v7 = load i32, i32* %v2, align 4
+  %v8 = add nsw i32 %v6, %v7
+  store i32 %v8, i32* %v0
+  br label %b3
 
-if.else:
-  %4 = load i32, i32* %a.addr, align 4
-  %5 = load i32, i32* %b.addr, align 4
-  %sub = sub nsw i32 %4, %5
-  store i32 %sub, i32* %retval
-  br label %return
+b2:                                               ; preds = %b0
+  %v9 = load i32, i32* %v1, align 4
+  %v10 = load i32, i32* %v2, align 4
+  %v11 = sub nsw i32 %v9, %v10
+  store i32 %v11, i32* %v0
+  br label %b3
 
-return:
-  %6 = load i32, i32* %retval
-  ret i32 %6
+b3:                                               ; preds = %b2, %b1
+  %v12 = load i32, i32* %v0
+  ret i32 %v12
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }