[Hexagon] Remove support for V4

llvm-svn: 344791

30 files changed, 1352 insertions, 1374 deletions

diff --git a/llvm/test/CodeGen/Hexagon/cfi-late.ll b/llvm/test/CodeGen/Hexagon/cfi-late.ll
index b5bdb59cc15..460b645b4a4 100644
--- a/llvm/test/CodeGen/Hexagon/cfi-late.ll
+++ b/llvm/test/CodeGen/Hexagon/cfi-late.ll
@@ -32,8 +32,8 @@ declare i32 @bar(i32, i32) #1
 ; Function Attrs: nounwind readnone
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
 
-attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
+attributes #1 = { "target-cpu"="hexagonv5" }
 attributes #2 = { nounwind readnone }
 attributes #3 = { nounwind }
 
diff --git a/llvm/test/CodeGen/Hexagon/double.ll b/llvm/test/CodeGen/Hexagon/double.ll
index b4d025cd7fd..336f32fee61 100644
--- a/llvm/test/CodeGen/Hexagon/double.ll
+++ b/llvm/test/CodeGen/Hexagon/double.ll
@@ -1,22 +1,24 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: __hexagon_adddf3
 ; CHECK: __hexagon_subdf3
 
-define void @foo(double* %acc, double %num, double %num2) nounwind {
-entry:
-  %acc.addr = alloca double*, align 4
-  %num.addr = alloca double, align 8
-  %num2.addr = alloca double, align 8
-  store double* %acc, double** %acc.addr, align 4
-  store double %num, double* %num.addr, align 8
-  store double %num2, double* %num2.addr, align 8
-  %0 = load double*, double** %acc.addr, align 4
-  %1 = load double, double* %0
-  %2 = load double, double* %num.addr, align 8
-  %add = fadd double %1, %2
-  %3 = load double, double* %num2.addr, align 8
-  %sub = fsub double %add, %3
-  %4 = load double*, double** %acc.addr, align 4
-  store double %sub, double* %4
+define void @f0(double* %a0, double %a1, double %a2) #0 {
+b0:
+  %v0 = alloca double*, align 4
+  %v1 = alloca double, align 8
+  %v2 = alloca double, align 8
+  store double* %a0, double** %v0, align 4
+  store double %a1, double* %v1, align 8
+  store double %a2, double* %v2, align 8
+  %v3 = load double*, double** %v0, align 4
+  %v4 = load double, double* %v3
+  %v5 = load double, double* %v1, align 8
+  %v6 = fadd double %v4, %v5
+  %v7 = load double, double* %v2, align 8
+  %v8 = fsub double %v6, %v7
+  %v9 = load double*, double** %v0, align 4
+  store double %v8, double* %v9
   ret void
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/float.ll b/llvm/test/CodeGen/Hexagon/float.ll
index 03d1fbf44cb..cc024a76d03 100644
--- a/llvm/test/CodeGen/Hexagon/float.ll
+++ b/llvm/test/CodeGen/Hexagon/float.ll
@@ -1,22 +1,24 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: __hexagon_addsf3
-; CHECK: __hexagon_subsf3
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: sfadd
+; CHECK: sfsub
 
-define void @foo(float* %acc, float %num, float %num2) nounwind {
-entry:
-  %acc.addr = alloca float*, align 4
-  %num.addr = alloca float, align 4
-  %num2.addr = alloca float, align 4
-  store float* %acc, float** %acc.addr, align 4
-  store float %num, float* %num.addr, align 4
-  store float %num2, float* %num2.addr, align 4
-  %0 = load float*, float** %acc.addr, align 4
-  %1 = load float, float* %0
-  %2 = load float, float* %num.addr, align 4
-  %add = fadd float %1, %2
-  %3 = load float, float* %num2.addr, align 4
-  %sub = fsub float %add, %3
-  %4 = load float*, float** %acc.addr, align 4
-  store float %sub, float* %4
+define void @f0(float* %a0, float %a1, float %a2) #0 {
+b0:
+  %v0 = alloca float*, align 4
+  %v1 = alloca float, align 4
+  %v2 = alloca float, align 4
+  store float* %a0, float** %v0, align 4
+  store float %a1, float* %v1, align 4
+  store float %a2, float* %v2, align 4
+  %v3 = load float*, float** %v0, align 4
+  %v4 = load float, float* %v3
+  %v5 = load float, float* %v1, align 4
+  %v6 = fadd float %v4, %v5
+  %v7 = load float, float* %v2, align 4
+  %v8 = fsub float %v6, %v7
+  %v9 = load float*, float** %v0, align 4
+  store float %v8, float* %v9
   ret void
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll b/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
index 03d1fbf44cb..cc024a76d03 100644
--- a/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
+++ b/llvm/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll
@@ -1,22 +1,24 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: __hexagon_addsf3
-; CHECK: __hexagon_subsf3
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: sfadd
+; CHECK: sfsub
 
-define void @foo(float* %acc, float %num, float %num2) nounwind {
-entry:
-  %acc.addr = alloca float*, align 4
-  %num.addr = alloca float, align 4
-  %num2.addr = alloca float, align 4
-  store float* %acc, float** %acc.addr, align 4
-  store float %num, float* %num.addr, align 4
-  store float %num2, float* %num2.addr, align 4
-  %0 = load float*, float** %acc.addr, align 4
-  %1 = load float, float* %0
-  %2 = load float, float* %num.addr, align 4
-  %add = fadd float %1, %2
-  %3 = load float, float* %num2.addr, align 4
-  %sub = fsub float %add, %3
-  %4 = load float*, float** %acc.addr, align 4
-  store float %sub, float* %4
+define void @f0(float* %a0, float %a1, float %a2) #0 {
+b0:
+  %v0 = alloca float*, align 4
+  %v1 = alloca float, align 4
+  %v2 = alloca float, align 4
+  store float* %a0, float** %v0, align 4
+  store float %a1, float* %v1, align 4
+  store float %a2, float* %v2, align 4
+  %v3 = load float*, float** %v0, align 4
+  %v4 = load float, float* %v3
+  %v5 = load float, float* %v1, align 4
+  %v6 = fadd float %v4, %v5
+  %v7 = load float, float* %v2, align 4
+  %v8 = fsub float %v6, %v7
+  %v9 = load float*, float** %v0, align 4
+  store float %v8, float* %v9
   ret void
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll b/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
index 57783d421a4..2514d4109c0 100644
--- a/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
+++ b/llvm/test/CodeGen/Hexagon/gp-plus-offset-load.ll
@@ -1,51 +1,57 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we generate load instructions with global + offset
 
-%struct.struc = type { i8, i8, i16, i32 }
 
-@foo = common global %struct.struc zeroinitializer, align 4
+%s.0 = type { i8, i8, i16, i32 }
 
-define void @loadWord(i32 %val1, i32 %val2, i32* nocapture %ival) nounwind {
-; CHECK: r{{[0-9]+}} = memw(##foo+4)
-entry:
-  %cmp = icmp sgt i32 %val1, %val2
-  br i1 %cmp, label %if.then, label %if.end
+@g0 = common global %s.0 zeroinitializer, align 4
 
-if.then:                                          ; preds = %entry
-  %0 = load i32, i32* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 3), align 4
-  store i32 %0, i32* %ival, align 4
-  br label %if.end
+; CHECK-LABEL: f0:
+; CHECK: r{{[0-9]+}} = memw(##g0+4)
+define void @f0(i32 %a0, i32 %a1, i32* nocapture %a2) #0 {
+b0:
+  %v0 = icmp sgt i32 %a0, %a1
+  br i1 %v0, label %b1, label %b2
 
-if.end:                                           ; preds = %if.then, %entry
+b1:                                               ; preds = %b0
+  %v1 = load i32, i32* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 3), align 4
+  store i32 %v1, i32* %a2, align 4
+  br label %b2
+
+b2:                                               ; preds = %b1, %b0
   ret void
 }
 
-define void @loadByte(i32 %val1, i32 %val2, i8* nocapture %ival) nounwind {
-; CHECK: r{{[0-9]+}} = memub(##foo+1)
-entry:
-  %cmp = icmp sgt i32 %val1, %val2
-  br i1 %cmp, label %if.then, label %if.end
+; CHECK-LABEL: f1:
+; CHECK: r{{[0-9]+}} = memub(##g0+1)
+define void @f1(i32 %a0, i32 %a1, i8* nocapture %a2) #0 {
+b0:
+  %v0 = icmp sgt i32 %a0, %a1
+  br i1 %v0, label %b1, label %b2
 
-if.then:                                          ; preds = %entry
-  %0 = load i8, i8* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 1), align 1
-  store i8 %0, i8* %ival, align 1
-  br label %if.end
+b1:                                               ; preds = %b0
+  %v1 = load i8, i8* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 1), align 1
+  store i8 %v1, i8* %a2, align 1
+  br label %b2
 
-if.end:                                           ; preds = %if.then, %entry
+b2:                                               ; preds = %b1, %b0
   ret void
 }
 
-define void @loadHWord(i32 %val1, i32 %val2, i16* %ival) nounwind {
-; CHECK: r{{[0-9]+}} = memuh(##foo+2)
-entry:
-  %cmp = icmp sgt i32 %val1, %val2
-  br i1 %cmp, label %if.then, label %if.end
+; CHECK-LABEL: f2:
+; CHECK: r{{[0-9]+}} = memuh(##g0+2)
+define void @f2(i32 %a0, i32 %a1, i16* %a2) #0 {
+b0:
+  %v0 = icmp sgt i32 %a0, %a1
+  br i1 %v0, label %b1, label %b2
 
-if.then:                                          ; preds = %entry
-  %0 = load i16, i16* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 2), align 2
-  store i16 %0, i16* %ival, align 2
-  br label %if.end
+b1:                                               ; preds = %b0
+  %v1 = load i16, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 2
+  store i16 %v1, i16* %a2, align 2
+  br label %b2
 
-if.end:                                           ; preds = %if.then, %entry
+b2:                                               ; preds = %b1, %b0
   ret void
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll b/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
index 66391b954d0..91e412f7c13 100644
--- a/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
+++ b/llvm/test/CodeGen/Hexagon/gp-plus-offset-store.ll
@@ -1,35 +1,38 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we generate store instructions with global + offset
 
-%struct.struc = type { i8, i8, i16, i32 }
+%s.0 = type { i8, i8, i16, i32 }
 
-@foo = common global %struct.struc zeroinitializer, align 4
+@g0 = common global %s.0 zeroinitializer, align 4
 
-define void @storeByte(i32 %val1, i32 %val2, i8 zeroext %ival) nounwind {
-; CHECK: memb(##foo+1) = r{{[0-9]+}}
-entry:
-  %cmp = icmp sgt i32 %val1, %val2
-  br i1 %cmp, label %if.then, label %if.end
+; CHECK-LABEL: f0:
+; CHECK: memb(##g0+1) = r{{[0-9]+}}
+define void @f0(i32 %a0, i32 %a1, i8 zeroext %a2) #0 {
+b0:
+  %v0 = icmp sgt i32 %a0, %a1
+  br i1 %v0, label %b1, label %b2
 
-if.then:                                          ; preds = %entry
-  store i8 %ival, i8* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 1), align 1
-  br label %if.end
+b1:                                               ; preds = %b0
+  store i8 %a2, i8* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 1), align 1
+  br label %b2
 
-if.end:                                           ; preds = %if.then, %entry
+b2:                                               ; preds = %b1, %b0
   ret void
 }
 
-define void @storeHW(i32 %val1, i32 %val2, i16 signext %ival) nounwind {
-; CHECK: memh(##foo+2) = r{{[0-9]+}}
-entry:
-  %cmp = icmp sgt i32 %val1, %val2
-  br i1 %cmp, label %if.then, label %if.end
+; CHECK-LABEL: f1:
+; CHECK: memh(##g0+2) = r{{[0-9]+}}
+define void @f1(i32 %a0, i32 %a1, i16 signext %a2) #0 {
+b0:
+  %v0 = icmp sgt i32 %a0, %a1
+  br i1 %v0, label %b1, label %b2
 
-if.then:                                          ; preds = %entry
-  store i16 %ival, i16* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 2), align 2
-  br label %if.end
+b1:                                               ; preds = %b0
+  store i16 %a2, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 2
+  br label %b2
 
-if.end:                                           ; preds = %if.then, %entry
+b2:                                               ; preds = %b1, %b0
   ret void
 }
 
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/gp-rel.ll b/llvm/test/CodeGen/Hexagon/gp-rel.ll
index ef913134f7c..3ce40bb5470 100644
--- a/llvm/test/CodeGen/Hexagon/gp-rel.ll
+++ b/llvm/test/CodeGen/Hexagon/gp-rel.ll
@@ -1,33 +1,36 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that gp-relative instructions are being generated.
 
-@a = common global i32 0, align 4
-@b = common global i32 0, align 4
-@c = common global i32 0, align 4
+; CHECK: r{{[0-9]+}} = memw(gp+#g0)
+; CHECK: r{{[0-9]+}} = memw(gp+#g1)
+; CHECK: if (p{{[0-3]}}) memw(##g2) = r{{[0-9]+}}
 
-define i32 @foo(i32 %p) #0 {
-entry:
-; CHECK: r{{[0-9]+}} = memw(gp+#a)
-; CHECK: r{{[0-9]+}} = memw(gp+#b)
-; CHECK: if (p{{[0-3]}}) memw(##c) = r{{[0-9]+}}
-  %0 = load i32, i32* @a, align 4
-  %1 = load i32, i32* @b, align 4
-  %add = add nsw i32 %1, %0
-  %cmp = icmp eq i32 %0, %1
-  br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
+@g0 = common global i32 0, align 4
+@g1 = common global i32 0, align 4
+@g2 = common global i32 0, align 4
 
-entry.if.end_crit_edge:
-  %.pre = load i32, i32* @c, align 4
-  br label %if.end
+define i32 @f0(i32 %a0) #0 {
+b0:
+  %v0 = load i32, i32* @g0, align 4
+  %v1 = load i32, i32* @g1, align 4
+  %v2 = add nsw i32 %v1, %v0
+  %v3 = icmp eq i32 %v0, %v1
+  br i1 %v3, label %b2, label %b1
 
-if.then:
-  %add1 = add nsw i32 %add, %0
-  store i32 %add1, i32* @c, align 4
-  br label %if.end
+b1:                                               ; preds = %b0
+  %v4 = load i32, i32* @g2, align 4
+  br label %b3
 
-if.end:
-  %2 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %add1, %if.then ]
-  %cmp2 = icmp eq i32 %add, %2
-  %sel1 = select i1 %cmp2, i32 %2, i32 %1
-  ret i32 %sel1
+b2:                                               ; preds = %b0
+  %v5 = add nsw i32 %v2, %v0
+  store i32 %v5, i32* @g2, align 4
+  br label %b3
+
+b3:                                               ; preds = %b2, %b1
+  %v6 = phi i32 [ %v4, %b1 ], [ %v5, %b2 ]
+  %v7 = icmp eq i32 %v2, %v6
+  %v8 = select i1 %v7, i32 %v6, i32 %v1
+  ret i32 %v8
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll b/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll
index 56a6fedf81e..71e1bf10fe6 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-cleanup.ll
@@ -1,87 +1,91 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -no-phi-elim-live-out-early-exit \
-; RUN:    < %s | FileCheck %s
+; RUN: llc -march=hexagon -no-phi-elim-live-out-early-exit < %s | FileCheck %s
 ; Check that we remove the compare and induction variable instructions
 ; after generating hardware loops.
 ; Bug 6685.
 
+; CHECK-LABEL: f0:
 ; CHECK: loop0
 ; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1)
 ; CHECK-NOT: cmp.eq
 ; CHECK: endloop0
 
-define i32 @test1(i32* nocapture %b, i32 %n) nounwind readonly {
-entry:
-  %cmp1 = icmp sgt i32 %n, 0
-  br i1 %cmp1, label %for.body.preheader, label %for.end
+define i32 @f0(i32* nocapture %a0, i32 %a1) #0 {
+b0:
+  %v0 = icmp sgt i32 %a1, 0
+  br i1 %v0, label %b1, label %b4
 
-for.body.preheader:
-  br label %for.body
+b1:                                               ; preds = %b0
+  br label %b2
 
-for.body:                                         ; preds = %for.body.preheader, %for.body
-  %sum.03 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
-  %arrayidx.phi = phi i32* [ %arrayidx.inc, %for.body ], [ %b, %for.body.preheader ]
-  %i.02 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
-  %0 = load i32, i32* %arrayidx.phi, align 4
-  %add = add nsw i32 %0, %sum.03
-  %inc = add nsw i32 %i.02, 1
-  %exitcond = icmp eq i32 %inc, %n
-  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
-  br i1 %exitcond, label %for.end.loopexit, label %for.body
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %v5, %b2 ], [ 0, %b1 ]
+  %v2 = phi i32* [ %v8, %b2 ], [ %a0, %b1 ]
+  %v3 = phi i32 [ %v6, %b2 ], [ 0, %b1 ]
+  %v4 = load i32, i32* %v2, align 4
+  %v5 = add nsw i32 %v4, %v1
+  %v6 = add nsw i32 %v3, 1
+  %v7 = icmp eq i32 %v6, %a1
+  %v8 = getelementptr i32, i32* %v2, i32 1
+  br i1 %v7, label %b3, label %b2
 
-for.end.loopexit:
-  br label %for.end
+b3:                                               ; preds = %b2
+  br label %b4
 
-for.end:
-  %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.end.loopexit ]
-  ret i32 %sum.0.lcssa
+b4:                                               ; preds = %b3, %b0
+  %v9 = phi i32 [ 0, %b0 ], [ %v5, %b3 ]
+  ret i32 %v9
 }
 
 ; This test checks that that initial loop count value is removed.
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ={{.}}#40
 ; CHECK: loop0
 ; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1)
 ; CHECK-NOT: cmp.eq
 ; CHECK: endloop0
 
-define i32 @test2(i32* nocapture %b) nounwind readonly {
-entry:
-  br label %for.body
+define i32 @f1(i32* nocapture %a0) #0 {
+b0:
+  br label %b1
 
-for.body:
-  %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ]
-  %arrayidx.phi = phi i32* [ %b, %entry ], [ %arrayidx.inc, %for.body ]
-  %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %0 = load i32, i32* %arrayidx.phi, align 4
-  %add = add nsw i32 %0, %sum.02
-  %inc = add nsw i32 %i.01, 1
-  %exitcond = icmp eq i32 %inc, 40
-  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
-  br i1 %exitcond, label %for.end, label %for.body
+b1:                                               ; preds = %b1, %b0
+  %v0 = phi i32 [ 0, %b0 ], [ %v4, %b1 ]
+  %v1 = phi i32* [ %a0, %b0 ], [ %v7, %b1 ]
+  %v2 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
+  %v3 = load i32, i32* %v1, align 4
+  %v4 = add nsw i32 %v3, %v0
+  %v5 = add nsw i32 %v2, 1
+  %v6 = icmp eq i32 %v5, 40
+  %v7 = getelementptr i32, i32* %v1, i32 1
+  br i1 %v6, label %b2, label %b1
 
-for.end:
-  ret i32 %add
+b2:                                               ; preds = %b1
+  ret i32 %v4
 }
 
 ; This test checks that we don't remove the induction variable since it's used.
+; CHECK-LABEL: f2:
 ; CHECK: loop0
 ; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},#1)
 ; CHECK-NOT: cmp.eq
 ; CHECK: endloop0
-define i32 @test3(i32* nocapture %b) nounwind {
-entry:
-  br label %for.body
 
-for.body:
-  %arrayidx.phi = phi i32* [ %b, %entry ], [ %arrayidx.inc, %for.body ]
-  %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  store i32 %i.01, i32* %arrayidx.phi, align 4
-  %inc = add nsw i32 %i.01, 1
-  %exitcond = icmp eq i32 %inc, 40
-  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
-  br i1 %exitcond, label %for.end, label %for.body
+define i32 @f2(i32* nocapture %a0) #1 {
+b0:
+  br label %b1
 
-for.end:
+b1:                                               ; preds = %b1, %b0
+  %v0 = phi i32* [ %a0, %b0 ], [ %v4, %b1 ]
+  %v1 = phi i32 [ 0, %b0 ], [ %v2, %b1 ]
+  store i32 %v1, i32* %v0, align 4
+  %v2 = add nsw i32 %v1, 1
+  %v3 = icmp eq i32 %v2, 40
+  %v4 = getelementptr i32, i32* %v0, i32 1
+  br i1 %v3, label %b2, label %b1
+
+b2:                                               ; preds = %b1
   ret i32 0
 }
 
-
+attributes #0 = { nounwind readonly "target-cpu"="hexagonv5" }
+attributes #1 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-const.ll b/llvm/test/CodeGen/Hexagon/hwloop-const.ll
index d549c1fef8c..eb105a33768 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-const.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-const.ll
@@ -1,27 +1,27 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -O2 < %s | FileCheck %s
-; ModuleID = 'hwloop-const.c'
-target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: endloop
+
 target triple = "hexagon-unknown-linux-gnu"
 
-@b = common global [25000 x i32] zeroinitializer, align 8
-@a = common global [25000 x i32] zeroinitializer, align 8
-@c = common global [25000 x i32] zeroinitializer, align 8
+@g0 = common global [25000 x i32] zeroinitializer, align 8
+@g1 = common global [25000 x i32] zeroinitializer, align 8
 
-define i32 @hwloop_bug() nounwind {
-entry:
-  br label %for.body
+define i32 @f0() #0 {
+b0:
+  br label %b1
 
-; CHECK: endloop
-for.body:                                         ; preds = %for.body, %entry
-  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds [25000 x i32], [25000 x i32]* @b, i32 0, i32 %i.02
-  store i32 %i.02, i32* %arrayidx, align 4
-  %arrayidx1 = getelementptr inbounds [25000 x i32], [25000 x i32]* @a, i32 0, i32 %i.02
-  store i32 %i.02, i32* %arrayidx1, align 4
-  %inc = add nsw i32 %i.02, 1
-  %exitcond = icmp eq i32 %inc, 25000
-  br i1 %exitcond, label %for.end, label %for.body
+b1:                                               ; preds = %b1, %b0
+  %v0 = phi i32 [ 0, %b0 ], [ %v3, %b1 ]
+  %v1 = getelementptr inbounds [25000 x i32], [25000 x i32]* @g0, i32 0, i32 %v0
+  store i32 %v0, i32* %v1, align 4
+  %v2 = getelementptr inbounds [25000 x i32], [25000 x i32]* @g1, i32 0, i32 %v0
+  store i32 %v0, i32* %v2, align 4
+  %v3 = add nsw i32 %v0, 1
+  %v4 = icmp eq i32 %v3, 25000
+  br i1 %v4, label %b2, label %b1
 
-for.end:                                          ; preds = %for.body
+b2:                                               ; preds = %b1
   ret i32 0
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll b/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll
index 10f3af73de1..443e4b59e9d 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-dbg.ll
@@ -1,63 +1,64 @@
-; RUN: llc < %s -march=hexagon -mcpu=hexagonv4 -O2 -disable-lsr | FileCheck %s
-; ModuleID = 'hwloop-dbg.o'
-target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
-target triple = "hexagon"
-
-define void @foo(i32* nocapture %a, i32* nocapture %b) nounwind !dbg !5 {
-entry:
-  tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !13, metadata !DIExpression()), !dbg !17
-  tail call void @llvm.dbg.value(metadata i32* %b, i64 0, metadata !14, metadata !DIExpression()), !dbg !18
-  tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !15, metadata !DIExpression()), !dbg !19
-  br label %for.body, !dbg !19
+; RUN: llc < %s -march=hexagon -disable-lsr | FileCheck %s
 
-for.body:                                         ; preds = %for.body, %entry
 ; CHECK:     loop0(
 ; CHECK-NOT: add({{r[0-9]*}}, #
 ; CHECK:     endloop0
-  %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
-  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
-  %b.addr.01 = phi i32* [ %b, %entry ], [ %incdec.ptr, %for.body ]
-  %incdec.ptr = getelementptr inbounds i32, i32* %b.addr.01, i32 1, !dbg !21
-  tail call void @llvm.dbg.value(metadata i32* %incdec.ptr, i64 0, metadata !14, metadata !DIExpression()), !dbg !21
-  %0 = load i32, i32* %b.addr.01, align 4, !dbg !21
-  store i32 %0, i32* %arrayidx.phi, align 4, !dbg !21
-  %inc = add nsw i32 %i.02, 1, !dbg !26
-  tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !15, metadata !DIExpression()), !dbg !26
-  %exitcond = icmp eq i32 %inc, 10, !dbg !19
-  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
-  br i1 %exitcond, label %for.end, label %for.body, !dbg !19
-
-for.end:                                          ; preds = %for.body
-  ret void, !dbg !27
+
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define void @f0(i32* nocapture %a0, i32* nocapture %a1) #0 !dbg !4 {
+b0:
+  call void @llvm.dbg.value(metadata i32* %a0, metadata !10, metadata !DIExpression()), !dbg !14
+  call void @llvm.dbg.value(metadata i32* %a1, metadata !11, metadata !DIExpression()), !dbg !15
+  call void @llvm.dbg.value(metadata i32 0, metadata !12, metadata !DIExpression()), !dbg !16
+  br label %b1, !dbg !16
+
+b1:                                               ; preds = %b1, %b0
+  %v0 = phi i32* [ %a0, %b0 ], [ %v7, %b1 ]
+  %v1 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
+  %v2 = phi i32* [ %a1, %b0 ], [ %v3, %b1 ]
+  %v3 = getelementptr inbounds i32, i32* %v2, i32 1, !dbg !18
+  call void @llvm.dbg.value(metadata i32* %v3, metadata !11, metadata !DIExpression()), !dbg !18
+  %v4 = load i32, i32* %v2, align 4, !dbg !18
+  store i32 %v4, i32* %v0, align 4, !dbg !18
+  %v5 = add nsw i32 %v1, 1, !dbg !20
+  call void @llvm.dbg.value(metadata i32 %v5, metadata !12, metadata !DIExpression()), !dbg !20
+  %v6 = icmp eq i32 %v5, 10, !dbg !16
+  %v7 = getelementptr i32, i32* %v0, i32 1
+  br i1 %v6, label %b2, label %b1, !dbg !16
+
+b2:                                               ; preds = %b1
+  ret void, !dbg !21
 }
 
-declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone
+declare void @llvm.dbg.value(metadata, metadata, metadata) #1
 
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
+attributes #1 = { nounwind readnone speculatable }
 
 !llvm.dbg.cu = !{!0}
-!llvm.module.flags = !{!29}
+!llvm.module.flags = !{!3}
 
-!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", isOptimized: true, emissionKind: FullDebug, file: !28, enums: !2, retainedTypes: !2, globals: !2)
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "QuIC LLVM Hexagon Clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2)
+!1 = !DIFile(filename: "hwloop-dbg.c", directory: "/test")
 !2 = !{}
-!5 = distinct !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 1, file: !28, scope: null, type: !7, retainedNodes: !11)
-!6 = !DIFile(filename: "hwloop-dbg.c", directory: "/usr2/kparzysz/s.hex/t")
-!7 = !DISubroutineType(types: !8)
-!8 = !{null, !9, !9}
-!9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !10)
-!10 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
-!11 = !{!13, !14, !15}
-!13 = !DILocalVariable(name: "a", line: 1, arg: 1, scope: !5, file: !6, type: !9)
-!14 = !DILocalVariable(name: "b", line: 1, arg: 2, scope: !5, file: !6, type: !9)
-!15 = !DILocalVariable(name: "i", line: 2, scope: !16, file: !6, type: !10)
-!16 = distinct !DILexicalBlock(line: 1, column: 26, file: !28, scope: !5)
-!17 = !DILocation(line: 1, column: 15, scope: !5)
-!18 = !DILocation(line: 1, column: 23, scope: !5)
-!19 = !DILocation(line: 3, column: 8, scope: !20)
-!20 = distinct !DILexicalBlock(line: 3, column: 3, file: !28, scope: !16)
-!21 = !DILocation(line: 4, column: 5, scope: !22)
-!22 = distinct !DILexicalBlock(line: 3, column: 28, file: !28, scope: !20)
-!26 = !DILocation(line: 3, column: 23, scope: !20)
-!27 = !DILocation(line: 6, column: 1, scope: !16)
-!28 = !DIFile(filename: "hwloop-dbg.c", directory: "/usr2/kparzysz/s.hex/t")
-!29 = !{i32 1, !"Debug Info Version", i32 3}
-!30 = !{i32 0}
+!3 = !{i32 1, !"Debug Info Version", i32 3}
+!4 = distinct !DISubprogram(name: "foo", scope: null, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 1, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !9)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null, !7, !7}
+!7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 32, align: 32)
+!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!9 = !{!10, !11, !12}
+!10 = !DILocalVariable(name: "a", arg: 1, scope: !4, file: !1, line: 1, type: !7)
+!11 = !DILocalVariable(name: "b", arg: 2, scope: !4, file: !1, line: 1, type: !7)
+!12 = !DILocalVariable(name: "i", scope: !13, file: !1, line: 2, type: !8)
+!13 = distinct !DILexicalBlock(scope: !4, file: !1, line: 1, column: 26)
+!14 = !DILocation(line: 1, column: 15, scope: !4)
+!15 = !DILocation(line: 1, column: 23, scope: !4)
+!16 = !DILocation(line: 3, column: 8, scope: !17)
+!17 = distinct !DILexicalBlock(scope: !13, file: !1, line: 3, column: 3)
+!18 = !DILocation(line: 4, column: 5, scope: !19)
+!19 = distinct !DILexicalBlock(scope: !17, file: !1, line: 3, column: 28)
+!20 = !DILocation(line: 3, column: 23, scope: !17)
+!21 = !DILocation(line: 6, column: 1, scope: !13)
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-le.ll b/llvm/test/CodeGen/Hexagon/hwloop-le.ll
index 85a1b3db673..d78b234d4ec 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-le.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-le.ll
@@ -1,438 +1,408 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
 
-
-; CHECK: test_pos1_ir_sle
+; CHECK-LABEL: f0:
 ; CHECK: loop0
 ; a < b
-define void @test_pos1_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 28395, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 28395, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 1
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f0(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 28395, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 28395, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 1
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos2_ir_sle
+; CHECK-LABEL: f1:
 ; CHECK: loop0
 ; a < b
-define void @test_pos2_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 9073, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 9073, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 2
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f1(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 9073, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 9073, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 2
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos4_ir_sle
+; CHECK-LABEL: f2:
 ; CHECK: loop0
 ; a < b
-define void @test_pos4_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 21956, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 21956, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 4
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f2(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 21956, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 21956, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 4
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos8_ir_sle
+; CHECK-LABEL: f3:
 ; CHECK: loop0
 ; a < b
-define void @test_pos8_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 16782, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 16782, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 8
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f3(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 16782, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 16782, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 8
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos16_ir_sle
+; CHECK-LABEL: f4:
 ; CHECK: loop0
 ; a < b
-define void @test_pos16_ir_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 19097, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 19097, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 16
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f4(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 19097, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 19097, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 16
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos1_ri_sle
+; CHECK-LABEL: f5:
 ; CHECK: loop0
 ; a < b
-define void @test_pos1_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, 14040
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 1
-  %cmp = icmp sle i32 %inc, 14040
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f5(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, 14040
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 1
+  %v8 = icmp sle i32 %v7, 14040
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos2_ri_sle
+; CHECK-LABEL: f6:
 ; CHECK: loop0
 ; a < b
-define void @test_pos2_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, 13710
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 2
-  %cmp = icmp sle i32 %inc, 13710
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f6(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, 13710
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 2
+  %v8 = icmp sle i32 %v7, 13710
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos4_ri_sle
+; CHECK-LABEL: f7:
 ; CHECK: loop0
 ; a < b
-define void @test_pos4_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, 9920
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 4
-  %cmp = icmp sle i32 %inc, 9920
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f7(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, 9920
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 4
+  %v8 = icmp sle i32 %v7, 9920
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos8_ri_sle
+; CHECK-LABEL: f8:
 ; CHECK: loop0
 ; a < b
-define void @test_pos8_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, 18924
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 8
-  %cmp = icmp sle i32 %inc, 18924
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f8(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, 18924
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 8
+  %v8 = icmp sle i32 %v7, 18924
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos16_ri_sle
+; CHECK-LABEL: f9:
 ; CHECK: loop0
 ; a < b
-define void @test_pos16_ri_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, 11812
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 16
-  %cmp = icmp sle i32 %inc, 11812
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f9(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, 11812
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 16
+  %v8 = icmp sle i32 %v7, 11812
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos1_rr_sle
+; CHECK-LABEL: f10:
 ; CHECK: loop0
 ; a < b
-define void @test_pos1_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 1
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f10(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 1
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos2_rr_sle
+; CHECK-LABEL: f11:
 ; CHECK: loop0
 ; a < b
-define void @test_pos2_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 2
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f11(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 2
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos4_rr_sle
+; CHECK-LABEL: f12:
 ; CHECK: loop0
 ; a < b
-define void @test_pos4_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 4
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f12(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 4
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos8_rr_sle
+; CHECK-LABEL: f13:
 ; CHECK: loop0
 ; a < b
-define void @test_pos8_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 8
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f13(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 8
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos16_rr_sle
+; CHECK-LABEL: f14:
 ; CHECK: loop0
 ; a < b
-define void @test_pos16_rr_sle(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp sle i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 16
-  %cmp = icmp sle i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f14(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sle i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 16
+  %v8 = icmp sle i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-ne.ll b/llvm/test/CodeGen/Hexagon/hwloop-ne.ll
index 12ef3b5dd0b..301a31a7c0b 100644
--- a/llvm/test/CodeGen/Hexagon/hwloop-ne.ll
+++ b/llvm/test/CodeGen/Hexagon/hwloop-ne.ll
@@ -1,438 +1,408 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
+; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
 
-
-; CHECK: test_pos1_ir_ne
+; CHECK-LABEL: f0:
 ; CHECK: loop0
 ; a < b
-define void @test_pos1_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 32623, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 32623, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 1
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f0(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 32623, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 32623, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 1
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos2_ir_ne
+; CHECK-LABEL: f1:
 ; CHECK: loop0
 ; a < b
-define void @test_pos2_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 29554, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 29554, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 2
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f1(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 29554, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 29554, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 2
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos4_ir_ne
+; CHECK-LABEL: f2:
 ; CHECK: loop0
 ; a < b
-define void @test_pos4_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 15692, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 15692, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 4
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f2(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 15692, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 15692, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 4
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos8_ir_ne
+; CHECK-LABEL: f3:
 ; CHECK: loop0
 ; a < b
-define void @test_pos8_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 10449, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 10449, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 8
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f3(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 10449, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 10449, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 8
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos16_ir_ne
+; CHECK-LABEL: f4:
 ; CHECK: loop0
 ; a < b
-define void @test_pos16_ir_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 32087, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ 32087, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 16
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f4(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 32087, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ 32087, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 16
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos1_ri_ne
+; CHECK-LABEL: f5:
 ; CHECK: loop0
 ; a < b
-define void @test_pos1_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, 3472
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 1
-  %cmp = icmp ne i32 %inc, 3472
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f5(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, 3472
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 1
+  %v8 = icmp ne i32 %v7, 3472
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos2_ri_ne
+; CHECK-LABEL: f6:
 ; CHECK: loop0
 ; a < b
-define void @test_pos2_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, 8730
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 2
-  %cmp = icmp ne i32 %inc, 8730
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f6(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, 8730
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 2
+  %v8 = icmp ne i32 %v7, 8730
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos4_ri_ne
+; CHECK-LABEL: f7:
 ; CHECK: loop0
 ; a < b
-define void @test_pos4_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, 1493
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 4
-  %cmp = icmp ne i32 %inc, 1493
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f7(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, 1493
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 4
+  %v8 = icmp ne i32 %v7, 1493
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos8_ri_ne
+; CHECK-LABEL: f8:
 ; CHECK: loop0
 ; a < b
-define void @test_pos8_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, 1706
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 8
-  %cmp = icmp ne i32 %inc, 1706
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f8(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, 1706
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 8
+  %v8 = icmp ne i32 %v7, 1706
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos16_ri_ne
+; CHECK-LABEL: f9:
 ; CHECK: loop0
 ; a < b
-define void @test_pos16_ri_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, 1886
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 16
-  %cmp = icmp ne i32 %inc, 1886
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f9(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, 1886
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 16
+  %v8 = icmp ne i32 %v7, 1886
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos1_rr_ne
+; CHECK-LABEL: f10:
 ; CHECK: loop0
 ; a < b
-define void @test_pos1_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 1
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f10(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 1
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos2_rr_ne
+; CHECK-LABEL: f11:
 ; CHECK: loop0
 ; a < b
-define void @test_pos2_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 2
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f11(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 2
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos4_rr_ne
+; CHECK-LABEL: f12:
 ; CHECK: loop0
 ; a < b
-define void @test_pos4_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 4
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f12(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 4
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos8_rr_ne
+; CHECK-LABEL: f13
 ; CHECK: loop0
 ; a < b
-define void @test_pos8_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 8
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f13(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 8
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
-; CHECK: test_pos16_rr_ne
+; CHECK-LABEL: f14
 ; CHECK: loop0
 ; a < b
-define void @test_pos16_rr_ne(i8* nocapture %p, i32 %a, i32 %b) nounwind {
-entry:
-  %cmp3 = icmp slt i32 %a, %b
-  br i1 %cmp3, label %for.body.lr.ph, label %for.end
-
-for.body.lr.ph:                                   ; preds = %entry
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.body
-  %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ]
-  %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04
-  %0 = load i8, i8* %arrayidx, align 1
-  %conv = zext i8 %0 to i32
-  %add = add nsw i32 %conv, 1
-  %conv1 = trunc i32 %add to i8
-  store i8 %conv1, i8* %arrayidx, align 1
-  %inc = add nsw i32 %i.04, 16
-  %cmp = icmp ne i32 %inc, %b
-  br i1 %cmp, label %for.body, label %for.end
-
-for.end:                                          ; preds = %for.body, %entry
+define void @f14(i8* nocapture %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp slt i32 %a1, %a2
+  br i1 %v0, label %b1, label %b3
+
+b1:                                               ; preds = %b0
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v1 = phi i32 [ %a1, %b1 ], [ %v7, %b2 ]
+  %v2 = getelementptr inbounds i8, i8* %a0, i32 %v1
+  %v3 = load i8, i8* %v2, align 1
+  %v4 = zext i8 %v3 to i32
+  %v5 = add nsw i32 %v4, 1
+  %v6 = trunc i32 %v5 to i8
+  store i8 %v6, i8* %v2, align 1
+  %v7 = add nsw i32 %v1, 16
+  %v8 = icmp ne i32 %v7, %a2
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
   ret void
 }
 
-
-
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/i16_VarArg.ll b/llvm/test/CodeGen/Hexagon/i16_VarArg.ll
index 74d066e4936..af2682edc4b 100644
--- a/llvm/test/CodeGen/Hexagon/i16_VarArg.ll
+++ b/llvm/test/CodeGen/Hexagon/i16_VarArg.ll
@@ -1,40 +1,36 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: call __hexagon_{{[A-Z_a-z0-9]+}}
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: dfcmp
 
-@a_str = internal constant [8 x i8] c"a = %f\0A\00"
-@b_str = internal constant [8 x i8] c"b = %f\0A\00"
-@add_str = internal constant [12 x i8] c"a + b = %f\0A\00"
-@sub_str = internal constant [12 x i8] c"a - b = %f\0A\00"
-@mul_str = internal constant [12 x i8] c"a * b = %f\0A\00"
-@div_str = internal constant [12 x i8] c"b / a = %f\0A\00"
-@rem_str = internal constant [13 x i8] c"b %% a = %f\0A\00"
-@lt_str = internal constant [12 x i8] c"a < b = %d\0A\00"
-@le_str = internal constant [13 x i8] c"a <= b = %d\0A\00"
-@gt_str = internal constant [12 x i8] c"a > b = %d\0A\00"
-@ge_str = internal constant [13 x i8] c"a >= b = %d\0A\00"
-@eq_str = internal constant [13 x i8] c"a == b = %d\0A\00"
-@ne_str = internal constant [13 x i8] c"a != b = %d\0A\00"
-@A = global double 2.000000e+00
-@B = global double 5.000000e+00
+@g0 = internal constant [12 x i8] c"a < b = %d\0A\00"
+@g1 = internal constant [13 x i8] c"a <= b = %d\0A\00"
+@g2 = internal constant [12 x i8] c"a > b = %d\0A\00"
+@g3 = internal constant [13 x i8] c"a >= b = %d\0A\00"
+@g4 = internal constant [13 x i8] c"a == b = %d\0A\00"
+@g5 = internal constant [13 x i8] c"a != b = %d\0A\00"
+@g6 = global double 2.000000e+00
+@g7 = global double 5.000000e+00
 
-declare i32 @printf(i8*, ...)
+declare i32 @f0(i8*, ...) #0
 
-define i32 @main() {
-        %a = load double, double* @A
-        %b = load double, double* @B
-        %lt_r = fcmp olt double %a, %b
-        %le_r = fcmp ole double %a, %b
-        %gt_r = fcmp ogt double %a, %b
-        %ge_r = fcmp oge double %a, %b
-        %eq_r = fcmp oeq double %a, %b
-        %ne_r = fcmp une double %a, %b
-        %val1 = zext i1 %lt_r to i16
-        %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0
-        %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0
-        %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0
-        %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0
-        %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0
-        %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0
-        call i32 (i8*, ...) @printf( i8* %lt_s, i16 %val1 )
-        ret i32 0
+define i32 @f1() #0 {
+b0:
+  %v0 = load double, double* @g6
+  %v1 = load double, double* @g7
+  %v2 = fcmp olt double %v0, %v1
+  %v3 = fcmp ole double %v0, %v1
+  %v4 = fcmp ogt double %v0, %v1
+  %v5 = fcmp oge double %v0, %v1
+  %v6 = fcmp oeq double %v0, %v1
+  %v7 = fcmp une double %v0, %v1
+  %v8 = zext i1 %v2 to i16
+  %v9 = getelementptr [12 x i8], [12 x i8]* @g0, i64 0, i64 0
+  %v10 = getelementptr [13 x i8], [13 x i8]* @g1, i64 0, i64 0
+  %v11 = getelementptr [12 x i8], [12 x i8]* @g2, i64 0, i64 0
+  %v12 = getelementptr [13 x i8], [13 x i8]* @g3, i64 0, i64 0
+  %v13 = getelementptr [13 x i8], [13 x i8]* @g4, i64 0, i64 0
+  %v14 = getelementptr [13 x i8], [13 x i8]* @g5, i64 0, i64 0
+  %v15 = call i32 (i8*, ...) @f0(i8* %v9, i16 %v8)
+  ret i32 0
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/i1_VarArg.ll b/llvm/test/CodeGen/Hexagon/i1_VarArg.ll
index 4078c0f3f00..01619bc5424 100644
--- a/llvm/test/CodeGen/Hexagon/i1_VarArg.ll
+++ b/llvm/test/CodeGen/Hexagon/i1_VarArg.ll
@@ -1,44 +1,40 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: call __hexagon_{{[_A-Za-z0-9]+}}
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: dfcmp
 
-@a_str = internal constant [8 x i8] c"a = %f\0A\00"
-@b_str = internal constant [8 x i8] c"b = %f\0A\00"
-@add_str = internal constant [12 x i8] c"a + b = %f\0A\00"
-@sub_str = internal constant [12 x i8] c"a - b = %f\0A\00"
-@mul_str = internal constant [12 x i8] c"a * b = %f\0A\00"
-@div_str = internal constant [12 x i8] c"b / a = %f\0A\00"
-@rem_str = internal constant [13 x i8] c"b %% a = %f\0A\00"
-@lt_str = internal constant [12 x i8] c"a < b = %d\0A\00"
-@le_str = internal constant [13 x i8] c"a <= b = %d\0A\00"
-@gt_str = internal constant [12 x i8] c"a > b = %d\0A\00"
-@ge_str = internal constant [13 x i8] c"a >= b = %d\0A\00"
-@eq_str = internal constant [13 x i8] c"a == b = %d\0A\00"
-@ne_str = internal constant [13 x i8] c"a != b = %d\0A\00"
-@A = global double 2.000000e+00
-@B = global double 5.000000e+00
+@g0 = internal constant [12 x i8] c"a < b = %d\0A\00"
+@g1 = internal constant [13 x i8] c"a <= b = %d\0A\00"
+@g2 = internal constant [12 x i8] c"a > b = %d\0A\00"
+@g3 = internal constant [13 x i8] c"a >= b = %d\0A\00"
+@g4 = internal constant [13 x i8] c"a == b = %d\0A\00"
+@g5 = internal constant [13 x i8] c"a != b = %d\0A\00"
+@g6 = global double 2.000000e+00
+@g7 = global double 5.000000e+00
 
-declare i32 @printf(i8*, ...)
+declare i32 @f0(i8*, ...) #0
 
-define i32 @main() {
-        %a = load double, double* @A
-        %b = load double, double* @B
-        %lt_r = fcmp olt double %a, %b
-        %le_r = fcmp ole double %a, %b
-        %gt_r = fcmp ogt double %a, %b
-        %ge_r = fcmp oge double %a, %b
-        %eq_r = fcmp oeq double %a, %b
-        %ne_r = fcmp une double %a, %b
-        %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0
-        %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0
-        %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0
-        %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0
-        %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0
-        %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0
-        call i32 (i8*, ...) @printf( i8* %lt_s, i1 %lt_r )
-        call i32 (i8*, ...) @printf( i8* %le_s, i1 %le_r )
-        call i32 (i8*, ...) @printf( i8* %gt_s, i1 %gt_r )
-        call i32 (i8*, ...) @printf( i8* %ge_s, i1 %ge_r )
-        call i32 (i8*, ...) @printf( i8* %eq_s, i1 %eq_r )
-        call i32 (i8*, ...) @printf( i8* %ne_s, i1 %ne_r )
-        ret i32 0
+define i32 @f1() #0 {
+b0:
+  %v0 = load double, double* @g6
+  %v1 = load double, double* @g7
+  %v2 = fcmp olt double %v0, %v1
+  %v3 = fcmp ole double %v0, %v1
+  %v4 = fcmp ogt double %v0, %v1
+  %v5 = fcmp oge double %v0, %v1
+  %v6 = fcmp oeq double %v0, %v1
+  %v7 = fcmp une double %v0, %v1
+  %v8 = getelementptr [12 x i8], [12 x i8]* @g0, i64 0, i64 0
+  %v9 = getelementptr [13 x i8], [13 x i8]* @g1, i64 0, i64 0
+  %v10 = getelementptr [12 x i8], [12 x i8]* @g2, i64 0, i64 0
+  %v11 = getelementptr [13 x i8], [13 x i8]* @g3, i64 0, i64 0
+  %v12 = getelementptr [13 x i8], [13 x i8]* @g4, i64 0, i64 0
+  %v13 = getelementptr [13 x i8], [13 x i8]* @g5, i64 0, i64 0
+  %v14 = call i32 (i8*, ...) @f0(i8* %v8, i1 %v2)
+  %v15 = call i32 (i8*, ...) @f0(i8* %v9, i1 %v3)
+  %v16 = call i32 (i8*, ...) @f0(i8* %v10, i1 %v4)
+  %v17 = call i32 (i8*, ...) @f0(i8* %v11, i1 %v5)
+  %v18 = call i32 (i8*, ...) @f0(i8* %v12, i1 %v6)
+  %v19 = call i32 (i8*, ...) @f0(i8* %v13, i1 %v7)
+  ret i32 0
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/i8_VarArg.ll b/llvm/test/CodeGen/Hexagon/i8_VarArg.ll
index 1353de47a97..247952d0c5c 100644
--- a/llvm/test/CodeGen/Hexagon/i8_VarArg.ll
+++ b/llvm/test/CodeGen/Hexagon/i8_VarArg.ll
@@ -1,40 +1,36 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: call __hexagon_{{[A-Z_a-z0-9]+}}
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: dfcmp
 
-@a_str = internal constant [8 x i8] c"a = %f\0A\00"
-@b_str = internal constant [8 x i8] c"b = %f\0A\00"
-@add_str = internal constant [12 x i8] c"a + b = %f\0A\00"
-@sub_str = internal constant [12 x i8] c"a - b = %f\0A\00"
-@mul_str = internal constant [12 x i8] c"a * b = %f\0A\00"
-@div_str = internal constant [12 x i8] c"b / a = %f\0A\00"
-@rem_str = internal constant [13 x i8] c"b %% a = %f\0A\00"
-@lt_str = internal constant [12 x i8] c"a < b = %d\0A\00"
-@le_str = internal constant [13 x i8] c"a <= b = %d\0A\00"
-@gt_str = internal constant [12 x i8] c"a > b = %d\0A\00"
-@ge_str = internal constant [13 x i8] c"a >= b = %d\0A\00"
-@eq_str = internal constant [13 x i8] c"a == b = %d\0A\00"
-@ne_str = internal constant [13 x i8] c"a != b = %d\0A\00"
-@A = global double 2.000000e+00
-@B = global double 5.000000e+00
+@g0 = internal constant [12 x i8] c"a < b = %d\0A\00"
+@g1 = internal constant [13 x i8] c"a <= b = %d\0A\00"
+@g2 = internal constant [12 x i8] c"a > b = %d\0A\00"
+@g3 = internal constant [13 x i8] c"a >= b = %d\0A\00"
+@g4 = internal constant [13 x i8] c"a == b = %d\0A\00"
+@g5 = internal constant [13 x i8] c"a != b = %d\0A\00"
+@g6 = global double 2.000000e+00
+@g7 = global double 5.000000e+00
 
-declare i32 @printf(i8*, ...)
+declare i32 @f0(i8*, ...) #0
 
-define i32 @main() {
-        %a = load double, double* @A
-        %b = load double, double* @B
-        %lt_r = fcmp olt double %a, %b
-        %le_r = fcmp ole double %a, %b
-        %gt_r = fcmp ogt double %a, %b
-        %ge_r = fcmp oge double %a, %b
-        %eq_r = fcmp oeq double %a, %b
-        %ne_r = fcmp une double %a, %b
-        %val1 = zext i1 %lt_r to i8
-        %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0
-        %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0
-        %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0
-        %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0
-        %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0
-        %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0
-        call i32 (i8*, ...) @printf( i8* %lt_s, i8 %val1 )
-        ret i32 0
+define i32 @f1() #0 {
+b0:
+  %v0 = load double, double* @g6
+  %v1 = load double, double* @g7
+  %v2 = fcmp olt double %v0, %v1
+  %v3 = fcmp ole double %v0, %v1
+  %v4 = fcmp ogt double %v0, %v1
+  %v5 = fcmp oge double %v0, %v1
+  %v6 = fcmp oeq double %v0, %v1
+  %v7 = fcmp une double %v0, %v1
+  %v8 = zext i1 %v2 to i8
+  %v9 = getelementptr [12 x i8], [12 x i8]* @g0, i64 0, i64 0
+  %v10 = getelementptr [13 x i8], [13 x i8]* @g1, i64 0, i64 0
+  %v11 = getelementptr [12 x i8], [12 x i8]* @g2, i64 0, i64 0
+  %v12 = getelementptr [13 x i8], [13 x i8]* @g3, i64 0, i64 0
+  %v13 = getelementptr [13 x i8], [13 x i8]* @g4, i64 0, i64 0
+  %v14 = getelementptr [13 x i8], [13 x i8]* @g5, i64 0, i64 0
+  %v15 = call i32 (i8*, ...) @f0(i8* %v9, i8 %v8)
+  ret i32 0
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/macint.ll b/llvm/test/CodeGen/Hexagon/macint.ll
index 514ba5b9130..47856f2fcb5 100644
--- a/llvm/test/CodeGen/Hexagon/macint.ll
+++ b/llvm/test/CodeGen/Hexagon/macint.ll
@@ -1,14 +1,15 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4  < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we generate integer multiply accumulate.
 
 ; CHECK: r{{[0-9]+}} {{\+|\-}}= mpyi(r{{[0-9]+}},
 
-define i32 @main(i32* %a, i32* %b) nounwind {
-  entry:
-  %0 = load i32, i32* %a, align 4
-  %div = udiv i32 %0, 10000
-  %rem = urem i32 %div, 10
-  store i32 %rem, i32* %b, align 4
+define i32 @f0(i32* %a0, i32* %a1) #0 {
+b0:
+  %v0 = load i32, i32* %a0, align 4
+  %v1 = udiv i32 %v0, 10000
+  %v2 = urem i32 %v1, 10
+  store i32 %v2, i32* %a1, align 4
   ret i32 0
 }
 
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/misaligned-access.ll b/llvm/test/CodeGen/Hexagon/misaligned-access.ll
index f4b0cb9cb1e..7eb85ffcc22 100644
--- a/llvm/test/CodeGen/Hexagon/misaligned-access.ll
+++ b/llvm/test/CodeGen/Hexagon/misaligned-access.ll
@@ -1,16 +1,19 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s
+; RUN: llc -march=hexagon < %s
 ; Check that the mis-aligned load doesn't cause compiler to assert.
 
-declare i32 @_hi(i64) #1
-@temp1 = common global i32 0, align 4
+@g0 = common global i32 0, align 4
 
-define i32 @CSDRSEARCH_executeSearchManager() #0 {
-entry:
-  %temp = alloca i32, align 4
-  %0 = load i32, i32* @temp1, align 4
-  store i32 %0, i32* %temp, align 4
-  %1 = bitcast i32* %temp to i64*
-  %2 = load i64, i64* %1, align 8
-  %call = call i32 @_hi(i64 %2)
-  ret i32 %call
+declare i32 @f0(i64) #0
+
+define i32 @f1() #0 {
+b0:
+  %v0 = alloca i32, align 4
+  %v1 = load i32, i32* @g0, align 4
+  store i32 %v1, i32* %v0, align 4
+  %v2 = bitcast i32* %v0 to i64*
+  %v3 = load i64, i64* %v2, align 8
+  %v4 = call i32 @f0(i64 %v3)
+  ret i32 %v4
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/mpy.ll b/llvm/test/CodeGen/Hexagon/mpy.ll
index 3ecf7d46ccb..7c1e8c8d3f0 100644
--- a/llvm/test/CodeGen/Hexagon/mpy.ll
+++ b/llvm/test/CodeGen/Hexagon/mpy.ll
@@ -1,19 +1,21 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: += mpyi
 
-define void @foo(i32 %acc, i32 %num, i32 %num2) nounwind {
-entry:
-  %acc.addr = alloca i32, align 4
-  %num.addr = alloca i32, align 4
-  %num2.addr = alloca i32, align 4
-  store i32 %acc, i32* %acc.addr, align 4
-  store i32 %num, i32* %num.addr, align 4
-  store i32 %num2, i32* %num2.addr, align 4
-  %0 = load i32, i32* %num.addr, align 4
-  %1 = load i32, i32* %acc.addr, align 4
-  %mul = mul nsw i32 %0, %1
-  %2 = load i32, i32* %num2.addr, align 4
-  %add = add nsw i32 %mul, %2
-  store i32 %add, i32* %num.addr, align 4
+define void @f0(i32 %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = alloca i32, align 4
+  %v1 = alloca i32, align 4
+  %v2 = alloca i32, align 4
+  store i32 %a0, i32* %v0, align 4
+  store i32 %a1, i32* %v1, align 4
+  store i32 %a2, i32* %v2, align 4
+  %v3 = load i32, i32* %v1, align 4
+  %v4 = load i32, i32* %v0, align 4
+  %v5 = mul nsw i32 %v3, %v4
+  %v6 = load i32, i32* %v2, align 4
+  %v7 = add nsw i32 %v5, %v6
+  store i32 %v7, i32* %v1, align 4
   ret void
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump.ll b/llvm/test/CodeGen/Hexagon/newvaluejump.ll
index e1437f369c8..0697d297d71 100644
--- a/llvm/test/CodeGen/Hexagon/newvaluejump.ll
+++ b/llvm/test/CodeGen/Hexagon/newvaluejump.ll
@@ -1,33 +1,36 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we generate new value jump.
 
-@i = global i32 0, align 4
-@j = global i32 10, align 4
-
-define i32 @foo(i32 %a) nounwind {
-entry:
 ; CHECK: if (cmp.eq(r{{[0-9]+}}.new,#0)) jump{{.}}
-  %addr1 = alloca i32, align 4
-  %addr2 = alloca i32, align 4
-  %0 = load i32, i32* @i, align 4
-  store i32 %0, i32* %addr1, align 4
-  call void @bar(i32 1, i32 2)
-  %1 = load i32, i32* @j, align 4
-  %tobool = icmp ne i32 %1, 0
-  br i1 %tobool, label %if.then, label %if.else
-
-if.then:
-  call void @baz(i32 1, i32 2)
-  br label %if.end
-
-if.else:
-  call void @guy(i32 10, i32 20)
-  br label %if.end
-
-if.end:
+
+@g0 = global i32 0, align 4
+@g1 = global i32 10, align 4
+
+define i32 @f0(i32 %a0) #0 {
+b0:
+  %v0 = alloca i32, align 4
+  %v1 = alloca i32, align 4
+  %v2 = load i32, i32* @g0, align 4
+  store i32 %v2, i32* %v0, align 4
+  call void @f2(i32 1, i32 2)
+  %v3 = load i32, i32* @g1, align 4
+  %v4 = icmp ne i32 %v3, 0
+  br i1 %v4, label %b1, label %b2
+
+b1:                                               ; preds = %b0
+  call void @f3(i32 1, i32 2)
+  br label %b3
+
+b2:                                               ; preds = %b0
+  call void @f1(i32 10, i32 20)
+  br label %b3
+
+b3:                                               ; preds = %b2, %b1
   ret i32 0
 }
 
-declare void @guy(i32, i32)
-declare void @bar(i32, i32)
-declare void @baz(i32, i32)
+declare void @f1(i32, i32) #0
+declare void @f2(i32, i32) #0
+declare void @f3(i32, i32) #0
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll b/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll
index 1fc6e82959e..8dca8f28114 100644
--- a/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll
+++ b/llvm/test/CodeGen/Hexagon/packetize_cond_inst.ll
@@ -1,10 +1,8 @@
-; RUN: llc -mcpu=hexagonv4 -tail-dup-size=1 < %s | FileCheck %s
+; RUN: llc -march=hexagon -tail-dup-size=1 < %s | FileCheck %s
 
-target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
 target triple = "hexagon-unknown--elf"
 
 ; Make sure we put the two conditionally executed adds in a packet.
-; ifcnv_add:
 ;     {
 ;       p0 = cmp.gt(r2, r1)
 ;       if (!p0.new) r0 = add(r2, r1)
@@ -13,20 +11,23 @@ target triple = "hexagon-unknown--elf"
 ; CHECK: cmp
 ; CHECK-NEXT: add
 ; CHECK-NEXT: add
-define i32 @ifcnv_add(i32, i32, i32) nounwind readnone {
-  %4 = icmp sgt i32 %2, %1
-  br i1 %4, label %5, label %7
+define i32 @f0(i32 %a0, i32 %a1, i32 %a2) #0 {
+b0:
+  %v0 = icmp sgt i32 %a2, %a1
+  br i1 %v0, label %b1, label %b2
 
-; <label>:5                                       ; preds = %3
-  %6 = add nsw i32 %0, 10
-  br label %9
+b1:                                               ; preds = %b0
+  %v1 = add nsw i32 %a0, 10
+  br label %b3
 
-; <label>:7                                       ; preds = %3
-  %8 = add nsw i32 %2, %1
-  br label %9
+b2:                                               ; preds = %b0
+  %v2 = add nsw i32 %a2, %a1
+  br label %b3
 
-; <label>:9                                       ; preds = %7, %5
-  %10 = phi i32 [ %6, %5 ], [ %8, %7 ]
-  %11 = add nsw i32 %10, 1
-  ret i32 %11
+b3:                                               ; preds = %b2, %b1
+  %v3 = phi i32 [ %v1, %b1 ], [ %v2, %b2 ]
+  %v4 = add nsw i32 %v3, 1
+  ret i32 %v4
 }
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/postinc-load.ll b/llvm/test/CodeGen/Hexagon/postinc-load.ll
index 8d8c93d76bf..825e16976a5 100644
--- a/llvm/test/CodeGen/Hexagon/postinc-load.ll
+++ b/llvm/test/CodeGen/Hexagon/postinc-load.ll
@@ -1,29 +1,30 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; Check that post-increment load instructions are being generated.
 ; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}++#4)
 
-define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {
-entry:
-  br label %for.body
+define i32 @f0(i32* nocapture %a0, i16* nocapture %a1, i32 %a2) #0 {
+b0:
+  br label %b1
 
-for.body:
-  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
-  %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
-  %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]
-  %sum.03 = phi i32 [ 0, %entry ], [ %add2, %for.body ]
-  %0 = load i32, i32* %arrayidx.phi, align 4
-  %1 = load i16, i16* %arrayidx1.phi, align 2
-  %conv = sext i16 %1 to i32
-  %add = add i32 %0, %sum.03
-  %add2 = add i32 %add, %conv
-  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
-  %arrayidx1.inc = getelementptr i16, i16* %arrayidx1.phi, i32 1
-  %lsr.iv.next = add i32 %lsr.iv, -1
-  %exitcond = icmp eq i32 %lsr.iv.next, 0
-  br i1 %exitcond, label %for.end, label %for.body
+b1:                                               ; preds = %b1, %b0
+  %v0 = phi i32 [ %v11, %b1 ], [ 10, %b0 ]
+  %v1 = phi i32* [ %a0, %b0 ], [ %v9, %b1 ]
+  %v2 = phi i16* [ %a1, %b0 ], [ %v10, %b1 ]
+  %v3 = phi i32 [ 0, %b0 ], [ %v8, %b1 ]
+  %v4 = load i32, i32* %v1, align 4
+  %v5 = load i16, i16* %v2, align 2
+  %v6 = sext i16 %v5 to i32
+  %v7 = add i32 %v4, %v3
+  %v8 = add i32 %v7, %v6
+  %v9 = getelementptr i32, i32* %v1, i32 1
+  %v10 = getelementptr i16, i16* %v2, i32 1
+  %v11 = add i32 %v0, -1
+  %v12 = icmp eq i32 %v11, 0
+  br i1 %v12, label %b2, label %b1
 
-for.end:
-  ret i32 %add2
+b2:                                               ; preds = %b1
+  ret i32 %v8
 }
 
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/postinc-store.ll b/llvm/test/CodeGen/Hexagon/postinc-store.ll
index 276a7d8e0ff..2dabc7991e3 100644
--- a/llvm/test/CodeGen/Hexagon/postinc-store.ll
+++ b/llvm/test/CodeGen/Hexagon/postinc-store.ll
@@ -1,29 +1,30 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; Check that post-increment store instructions are being generated.
 ; CHECK: memw(r{{[0-9]+}}++#4) = r{{[0-9]+}}
 
-define i32 @sum(i32* nocapture %a, i16* nocapture %b, i32 %n) nounwind {
-entry:
-  br label %for.body
+define i32 @f0(i32* nocapture %a0, i16* nocapture %a1, i32 %a2) #0 {
+b0:
+  br label %b1
 
-for.body:                                         ; preds = %for.body, %entry
-  %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ]
-  %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ]
-  %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ]
-  %0 = load i32, i32* %arrayidx.phi, align 4
-  %1 = load i16, i16* %arrayidx1.phi, align 2
-  %conv = sext i16 %1 to i32
-  %factor = mul i32 %0, 2
-  %add3 = add i32 %factor, %conv
-  store i32 %add3, i32* %arrayidx.phi, align 4
+b1:                                               ; preds = %b1, %b0
+  %v0 = phi i32 [ %v10, %b1 ], [ 10, %b0 ]
+  %v1 = phi i32* [ %a0, %b0 ], [ %v8, %b1 ]
+  %v2 = phi i16* [ %a1, %b0 ], [ %v9, %b1 ]
+  %v3 = load i32, i32* %v1, align 4
+  %v4 = load i16, i16* %v2, align 2
+  %v5 = sext i16 %v4 to i32
+  %v6 = mul i32 %v3, 2
+  %v7 = add i32 %v6, %v5
+  store i32 %v7, i32* %v1, align 4
+  %v8 = getelementptr i32, i32* %v1, i32 1
+  %v9 = getelementptr i16, i16* %v2, i32 1
+  %v10 = add i32 %v0, -1
+  %v11 = icmp eq i32 %v10, 0
+  br i1 %v11, label %b2, label %b1
 
-  %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
-  %arrayidx1.inc = getelementptr i16, i16* %arrayidx1.phi, i32 1
-  %lsr.iv.next = add i32 %lsr.iv, -1
-  %exitcond = icmp eq i32 %lsr.iv.next, 0
-  br i1 %exitcond, label %for.end, label %for.body
-
-for.end:                                          ; preds = %for.body
+b2:                                               ; preds = %b1
   ret i32 0
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/pred-gp.ll b/llvm/test/CodeGen/Hexagon/pred-gp.ll
index 76a621699b6..4d50abf6283 100644
--- a/llvm/test/CodeGen/Hexagon/pred-gp.ll
+++ b/llvm/test/CodeGen/Hexagon/pred-gp.ll
@@ -1,28 +1,30 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we are able to predicate instructions with gp-relative
 ; addressing mode.
 
-@d = external global i32
-@c = common global i32 0, align 4
+; CHECK: if ({{!?}}p{{[0-3]+}}{{(.new)?}}) r{{[0-9]+}} = memw(##g{{[01]}})
+; CHECK: if ({{!?}}p{{[0-3]+}}) r{{[0-9]+}} = memw(##g{{[01]}})
 
-; Function Attrs: nounwind
-define i32 @test2(i8 zeroext %a, i8 zeroext %b) #0 {
-; CHECK: if ({{!?}}p{{[0-3]+}}{{(.new)?}}) r{{[0-9]+}} = memw(##{{[cd]}})
-; CHECK: if ({{!?}}p{{[0-3]+}}) r{{[0-9]+}} = memw(##{{[cd]}})
-entry:
-  %cmp = icmp eq i8 %a, %b
-  br i1 %cmp, label %if.then, label %entry.if.end_crit_edge
+@g0 = external global i32
+@g1 = common global i32 0, align 4
 
-entry.if.end_crit_edge:
-  %.pre = load i32, i32* @c, align 4
-  br label %if.end
+define i32 @f0(i8 zeroext %a0, i8 zeroext %a1) #0 {
+b0:
+  %v0 = icmp eq i8 %a0, %a1
+  br i1 %v0, label %b2, label %b1
 
-if.then:
-  %0 = load i32, i32* @d, align 4
-  store i32 %0, i32* @c, align 4
-  br label %if.end
+b1:                                               ; preds = %b0
+  %v1 = load i32, i32* @g1, align 4
+  br label %b3
 
-if.end:
-  %1 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %0, %if.then ]
-  ret i32 %1
+b2:                                               ; preds = %b0
+  %v2 = load i32, i32* @g0, align 4
+  store i32 %v2, i32* @g1, align 4
+  br label %b3
+
+b3:                                               ; preds = %b2, %b1
+  %v3 = phi i32 [ %v1, %b1 ], [ %v2, %b2 ]
+  ret i32 %v3
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/pred-instrs.ll b/llvm/test/CodeGen/Hexagon/pred-instrs.ll
index da8ace98a0b..27986f872d9 100644
--- a/llvm/test/CodeGen/Hexagon/pred-instrs.ll
+++ b/llvm/test/CodeGen/Hexagon/pred-instrs.ll
@@ -1,30 +1,32 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; Check that we are able to predicate instructions.
 
 ; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
 ; CHECK: if ({{!?}}p{{[0-3]}}{{(.new)?}}) r{{[0-9]+}} = {{and|aslh}}
-@a = external global i32
-@d = external global i32
 
-; Function Attrs: nounwind
-define i32 @test1(i8 zeroext %la, i8 zeroext %lb) {
-entry:
-  %cmp = icmp eq i8 %la, %lb
-  br i1 %cmp, label %if.then, label %if.else
+@g0 = external global i32
+@g1 = external global i32
 
-if.then:                                          ; preds = %entry
-  %conv1 = zext i8 %la to i32
-  %shl = shl nuw nsw i32 %conv1, 16
-  br label %if.end
+define i32 @f0(i8 zeroext %a0, i8 zeroext %a1) #0 {
+b0:
+  %v0 = icmp eq i8 %a0, %a1
+  br i1 %v0, label %b1, label %b2
 
-if.else:                                          ; preds = %entry
-  %and8 = and i8 %lb, %la
-  %and = zext i8 %and8 to i32
-  br label %if.end
+b1:                                               ; preds = %b0
+  %v1 = zext i8 %a0 to i32
+  %v2 = shl nuw nsw i32 %v1, 16
+  br label %b3
 
-if.end:                                           ; preds = %if.else, %if.then
-  %storemerge = phi i32 [ %and, %if.else ], [ %shl, %if.then ]
-  store i32 %storemerge, i32* @a, align 4
-  %0 = load i32, i32* @d, align 4
-  ret i32 %0
+b2:                                               ; preds = %b0
+  %v3 = and i8 %a1, %a0
+  %v4 = zext i8 %v3 to i32
+  br label %b3
+
+b3:                                               ; preds = %b2, %b1
+  %v5 = phi i32 [ %v4, %b2 ], [ %v2, %b1 ]
+  store i32 %v5, i32* @g0, align 4
+  %v6 = load i32, i32* @g1, align 4
+  ret i32 %v6
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/predicate-copy.ll b/llvm/test/CodeGen/Hexagon/predicate-copy.ll
index 552b6879419..1b58ec9e790 100644
--- a/llvm/test/CodeGen/Hexagon/predicate-copy.ll
+++ b/llvm/test/CodeGen/Hexagon/predicate-copy.ll
@@ -1,8 +1,10 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
+; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
 
 ; CHECK: r{{[0-9]+}} = p{{[0-9]+}}
-define i1 @foo() {
-entry:
+
+define i1 @f0() #0 {
+b0:
   ret i1 false
 }
 
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/remove_lsr.ll b/llvm/test/CodeGen/Hexagon/remove_lsr.ll
index 3b85c486348..dee384520e5 100644
--- a/llvm/test/CodeGen/Hexagon/remove_lsr.ll
+++ b/llvm/test/CodeGen/Hexagon/remove_lsr.ll
@@ -1,6 +1,6 @@
 ; Test fix for PR-13709.
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: foo
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: f0
 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
 ; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32)
 
@@ -13,64 +13,64 @@
 ; This makes the lsr instruction dead and it gets removed subsequently
 ; by a dead code removal pass.
 
-%union.vect64 = type { i64 }
-%union.vect32 = type { i32 }
 
-define void @foo(%union.vect64* nocapture %sss_extracted_bit_rx_data_ptr,
- %union.vect32* nocapture %s_even, %union.vect32* nocapture %s_odd,
- i8* nocapture %scr_s_even_code_ptr, i8* nocapture %scr_s_odd_code_ptr)
- nounwind {
-entry:
-  %scevgep = getelementptr %union.vect64, %union.vect64* %sss_extracted_bit_rx_data_ptr, i32 1
-  %scevgep28 = getelementptr %union.vect32, %union.vect32* %s_odd, i32 1
-  %scevgep32 = getelementptr %union.vect32, %union.vect32* %s_even, i32 1
-  %scevgep36 = getelementptr i8, i8* %scr_s_odd_code_ptr, i32 1
-  %scevgep39 = getelementptr i8, i8* %scr_s_even_code_ptr, i32 1
-  br label %for.body
+%s.0 = type { i64 }
+%s.1 = type { i32 }
 
-for.body:                                         ; preds = %for.body, %entry
-  %lsr.iv42 = phi i32 [ %lsr.iv.next, %for.body ], [ 2, %entry ]
-  %lsr.iv40 = phi i8* [ %scevgep41, %for.body ], [ %scevgep39, %entry ]
-  %lsr.iv37 = phi i8* [ %scevgep38, %for.body ], [ %scevgep36, %entry ]
-  %lsr.iv33 = phi %union.vect32* [ %scevgep34, %for.body ], [ %scevgep32, %entry ]
-  %lsr.iv29 = phi %union.vect32* [ %scevgep30, %for.body ], [ %scevgep28, %entry ]
-  %lsr.iv = phi %union.vect64* [ %scevgep26, %for.body ], [ %scevgep, %entry ]
-  %predicate_1.023 = phi i8 [ undef, %entry ], [ %10, %for.body ]
-  %predicate.022 = phi i8 [ undef, %entry ], [ %9, %for.body ]
-  %val.021 = phi i64 [ undef, %entry ], [ %srcval, %for.body ]
-  %lsr.iv3335 = bitcast %union.vect32* %lsr.iv33 to i32*
-  %lsr.iv2931 = bitcast %union.vect32* %lsr.iv29 to i32*
-  %lsr.iv27 = bitcast %union.vect64* %lsr.iv to i64*
-  %0 = tail call i64 @llvm.hexagon.A2.vsubhs(i64 0, i64 %val.021)
-  %conv3 = sext i8 %predicate.022 to i32
-  %1 = trunc i64 %val.021 to i32
-  %2 = trunc i64 %0 to i32
-  %3 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv3, i32 %1, i32 %2)
-  store i32 %3, i32* %lsr.iv3335, align 4
-  %conv8 = sext i8 %predicate_1.023 to i32
-  %4 = lshr i64 %val.021, 32
-  %5 = trunc i64 %4 to i32
-  %6 = lshr i64 %0, 32
-  %7 = trunc i64 %6 to i32
-  %8 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv8, i32 %5, i32 %7)
-  store i32 %8, i32* %lsr.iv2931, align 4
-  %srcval = load i64, i64* %lsr.iv27, align 8
-  %9 = load i8, i8* %lsr.iv40, align 1
-  %10 = load i8, i8* %lsr.iv37, align 1
-  %lftr.wideiv = trunc i32 %lsr.iv42 to i8
-  %exitcond = icmp eq i8 %lftr.wideiv, 32
-  %scevgep26 = getelementptr %union.vect64, %union.vect64* %lsr.iv, i32 1
-  %scevgep30 = getelementptr %union.vect32, %union.vect32* %lsr.iv29, i32 1
-  %scevgep34 = getelementptr %union.vect32, %union.vect32* %lsr.iv33, i32 1
-  %scevgep38 = getelementptr i8, i8* %lsr.iv37, i32 1
-  %scevgep41 = getelementptr i8, i8* %lsr.iv40, i32 1
-  %lsr.iv.next = add i32 %lsr.iv42, 1
-  br i1 %exitcond, label %for.end, label %for.body
+define void @f0(%s.0* nocapture %a0, %s.1* nocapture %a1, %s.1* nocapture %a2, i8* nocapture %a3, i8* nocapture %a4) #0 {
+b0:
+  %v0 = getelementptr %s.0, %s.0* %a0, i32 1
+  %v1 = getelementptr %s.1, %s.1* %a2, i32 1
+  %v2 = getelementptr %s.1, %s.1* %a1, i32 1
+  %v3 = getelementptr i8, i8* %a4, i32 1
+  %v4 = getelementptr i8, i8* %a3, i32 1
+  br label %b1
 
-for.end:                                          ; preds = %for.body
+b1:                                               ; preds = %b1, %b0
+  %v5 = phi i32 [ %v38, %b1 ], [ 2, %b0 ]
+  %v6 = phi i8* [ %v37, %b1 ], [ %v4, %b0 ]
+  %v7 = phi i8* [ %v36, %b1 ], [ %v3, %b0 ]
+  %v8 = phi %s.1* [ %v35, %b1 ], [ %v2, %b0 ]
+  %v9 = phi %s.1* [ %v34, %b1 ], [ %v1, %b0 ]
+  %v10 = phi %s.0* [ %v33, %b1 ], [ %v0, %b0 ]
+  %v11 = phi i8 [ undef, %b0 ], [ %v30, %b1 ]
+  %v12 = phi i8 [ undef, %b0 ], [ %v29, %b1 ]
+  %v13 = phi i64 [ undef, %b0 ], [ %v28, %b1 ]
+  %v14 = bitcast %s.1* %v8 to i32*
+  %v15 = bitcast %s.1* %v9 to i32*
+  %v16 = bitcast %s.0* %v10 to i64*
+  %v17 = tail call i64 @llvm.hexagon.A2.vsubhs(i64 0, i64 %v13)
+  %v18 = sext i8 %v12 to i32
+  %v19 = trunc i64 %v13 to i32
+  %v20 = trunc i64 %v17 to i32
+  %v21 = tail call i32 @llvm.hexagon.C2.mux(i32 %v18, i32 %v19, i32 %v20)
+  store i32 %v21, i32* %v14, align 4
+  %v22 = sext i8 %v11 to i32
+  %v23 = lshr i64 %v13, 32
+  %v24 = trunc i64 %v23 to i32
+  %v25 = lshr i64 %v17, 32
+  %v26 = trunc i64 %v25 to i32
+  %v27 = tail call i32 @llvm.hexagon.C2.mux(i32 %v22, i32 %v24, i32 %v26)
+  store i32 %v27, i32* %v15, align 4
+  %v28 = load i64, i64* %v16, align 8
+  %v29 = load i8, i8* %v6, align 1
+  %v30 = load i8, i8* %v7, align 1
+  %v31 = trunc i32 %v5 to i8
+  %v32 = icmp eq i8 %v31, 32
+  %v33 = getelementptr %s.0, %s.0* %v10, i32 1
+  %v34 = getelementptr %s.1, %s.1* %v9, i32 1
+  %v35 = getelementptr %s.1, %s.1* %v8, i32 1
+  %v36 = getelementptr i8, i8* %v7, i32 1
+  %v37 = getelementptr i8, i8* %v6, i32 1
+  %v38 = add i32 %v5, 1
+  br i1 %v32, label %b2, label %b1
+
+b2:                                               ; preds = %b1
   ret void
 }
 
-declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) nounwind readnone
+declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) #1
+declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) #1
 
-declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) nounwind readnone
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/simpletailcall.ll b/llvm/test/CodeGen/Hexagon/simpletailcall.ll
index 287640489a5..76854bc1981 100644
--- a/llvm/test/CodeGen/Hexagon/simpletailcall.ll
+++ b/llvm/test/CodeGen/Hexagon/simpletailcall.ll
@@ -1,14 +1,16 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: foo_empty
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: f0
 ; CHECK-NOT: allocframe
 ; CHECK-NOT: memd(r29
-; CHECK: jump bar_empty
+; CHECK: jump f1
 
-define void @foo_empty(i32 %h) nounwind {
-entry:
-  %add = add nsw i32 %h, 3
-  %call = tail call i32 bitcast (i32 (...)* @bar_empty to i32 (i32)*)(i32 %add) nounwind
+define void @f0(i32 %a0) #0 {
+b0:
+  %v0 = add nsw i32 %a0, 3
+  %v1 = tail call i32 bitcast (i32 (...)* @f1 to i32 (i32)*)(i32 %v0) #0
   ret void
 }
 
-declare i32 @bar_empty(...)
+declare i32 @f1(...) #0
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/union-1.ll b/llvm/test/CodeGen/Hexagon/union-1.ll
index 8f2ff28b381..970ded79deb 100644
--- a/llvm/test/CodeGen/Hexagon/union-1.ll
+++ b/llvm/test/CodeGen/Hexagon/union-1.ll
@@ -1,19 +1,21 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
-; CHECK: word
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: f0
 ; CHECK-NOT: combine(#0
-; CHECK: jump bar
+; CHECK: jump f1
 
-define void @word(i32* nocapture %a) nounwind {
-entry:
-  %0 = load i32, i32* %a, align 4
-  %1 = zext i32 %0 to i64
-  %add.ptr = getelementptr inbounds i32, i32* %a, i32 1
-  %2 = load i32, i32* %add.ptr, align 4
-  %3 = zext i32 %2 to i64
-  %4 = shl nuw i64 %3, 32
-  %ins = or i64 %4, %1
-  tail call void @bar(i64 %ins) nounwind
+define void @f0(i32* nocapture %a0) #0 {
+b0:
+  %v0 = load i32, i32* %a0, align 4
+  %v1 = zext i32 %v0 to i64
+  %v2 = getelementptr inbounds i32, i32* %a0, i32 1
+  %v3 = load i32, i32* %v2, align 4
+  %v4 = zext i32 %v3 to i64
+  %v5 = shl nuw i64 %v4, 32
+  %v6 = or i64 %v5, %v1
+  tail call void @f1(i64 %v6) #0
   ret void
 }
 
-declare void @bar(i64)
+declare void @f1(i64) #0
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/vaddh.ll b/llvm/test/CodeGen/Hexagon/vaddh.ll
index a4fb33de4ac..f139c288bb5 100644
--- a/llvm/test/CodeGen/Hexagon/vaddh.ll
+++ b/llvm/test/CodeGen/Hexagon/vaddh.ll
@@ -1,16 +1,19 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 ; CHECK: vaddh(r{{[0-9]+}},r{{[0-9]+}})
 
-@j = external global i32
-@k = external global i32
+@g0 = external global i32
+@g1 = external global i32
 
-define void @foo() nounwind {
-entry:
-  %0 = load i32, i32* @j, align 4
-  %1 = load i32, i32* @k, align 4
-  %2 = call i32 @llvm.hexagon.A2.svaddh(i32 %0, i32 %1)
-  store i32 %2, i32* @k, align 4
+define void @f0() #0 {
+b0:
+  %v0 = load i32, i32* @g0, align 4
+  %v1 = load i32, i32* @g1, align 4
+  %v2 = call i32 @llvm.hexagon.A2.svaddh(i32 %v0, i32 %v1)
+  store i32 %v2, i32* @g1, align 4
   ret void
 }
 
-declare i32 @llvm.hexagon.A2.svaddh(i32, i32) nounwind readnone
+declare i32 @llvm.hexagon.A2.svaddh(i32, i32) #1
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }
+attributes #1 = { nounwind readnone "target-cpu"="hexagonv5" }
diff --git a/llvm/test/CodeGen/Hexagon/validate-offset.ll b/llvm/test/CodeGen/Hexagon/validate-offset.ll
index 8de006c80b1..ed98f281e4b 100644
--- a/llvm/test/CodeGen/Hexagon/validate-offset.ll
+++ b/llvm/test/CodeGen/Hexagon/validate-offset.ll
@@ -1,36 +1,38 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s -O0
+; RUN: llc -march=hexagon -O0 < %s
 
 ; This is a regression test which makes sure that the offset check
 ; is available for STRiw_indexed instruction. This is required
 ; by 'Hexagon Expand Predicate Spill Code' pass.
 
-define i32 @f(i32 %a, i32 %b) nounwind {
-entry:
-  %retval = alloca i32, align 4
-  %a.addr = alloca i32, align 4
-  %b.addr = alloca i32, align 4
-  store i32 %a, i32* %a.addr, align 4
-  store i32 %b, i32* %b.addr, align 4
-  %0 = load i32, i32* %a.addr, align 4
-  %1 = load i32, i32* %b.addr, align 4
-  %cmp = icmp sgt i32 %0, %1
-  br i1 %cmp, label %if.then, label %if.else
+define i32 @f0(i32 %a0, i32 %a1) #0 {
+b0:
+  %v0 = alloca i32, align 4
+  %v1 = alloca i32, align 4
+  %v2 = alloca i32, align 4
+  store i32 %a0, i32* %v1, align 4
+  store i32 %a1, i32* %v2, align 4
+  %v3 = load i32, i32* %v1, align 4
+  %v4 = load i32, i32* %v2, align 4
+  %v5 = icmp sgt i32 %v3, %v4
+  br i1 %v5, label %b1, label %b2
 
-if.then:
-  %2 = load i32, i32* %a.addr, align 4
-  %3 = load i32, i32* %b.addr, align 4
-  %add = add nsw i32 %2, %3
-  store i32 %add, i32* %retval
-  br label %return
+b1:                                               ; preds = %b0
+  %v6 = load i32, i32* %v1, align 4
+  %v7 = load i32, i32* %v2, align 4
+  %v8 = add nsw i32 %v6, %v7
+  store i32 %v8, i32* %v0
+  br label %b3
 
-if.else:
-  %4 = load i32, i32* %a.addr, align 4
-  %5 = load i32, i32* %b.addr, align 4
-  %sub = sub nsw i32 %4, %5
-  store i32 %sub, i32* %retval
-  br label %return
+b2:                                               ; preds = %b0
+  %v9 = load i32, i32* %v1, align 4
+  %v10 = load i32, i32* %v2, align 4
+  %v11 = sub nsw i32 %v9, %v10
+  store i32 %v11, i32* %v0
+  br label %b3
 
-return:
-  %6 = load i32, i32* %retval
-  ret i32 %6
+b3:                                               ; preds = %b2, %b1
+  %v12 = load i32, i32* %v0
+  ret i32 %v12
 }
+
+attributes #0 = { nounwind "target-cpu"="hexagonv5" }