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| author | Dylan McKay <dylanmckay34@gmail.com> | 2016-10-08 01:01:49 +0000 |
|---|---|---|
| committer | Dylan McKay <dylanmckay34@gmail.com> | 2016-10-08 01:01:49 +0000 |
| commit | c1ff65cf62635fedb69fd360d9e292c03004c490 (patch) | |
| tree | 6823fa171a2c08e9292d315dd613de6816b12085 /llvm/test/CodeGen/AVR/umul-with-overflow.ll | |
| parent | b10fc3709609ecec4f615aa0f734266fc78721d1 (diff) | |
| download | bcm5719-llvm-c1ff65cf62635fedb69fd360d9e292c03004c490.tar.gz bcm5719-llvm-c1ff65cf62635fedb69fd360d9e292c03004c490.zip | |
[AVR] Expand MULHS for all types
Once MULHS was expanded, this exposed an issue where the condition
register was thought to be 16-bit. This caused an attempt to copy a
16-bit register to an 8-bit register.
Authored by Jake Goulding
llvm-svn: 283634
Diffstat (limited to 'llvm/test/CodeGen/AVR/umul-with-overflow.ll')
| -rw-r--r-- | llvm/test/CodeGen/AVR/umul-with-overflow.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AVR/umul-with-overflow.ll b/llvm/test/CodeGen/AVR/umul-with-overflow.ll new file mode 100644 index 00000000000..aa8b10a313d --- /dev/null +++ b/llvm/test/CodeGen/AVR/umul-with-overflow.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=avr | FileCheck %s + +define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr { +; CHECK-LABEL: unsigned_multiplication_did_overflow: +entry-block: + %2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1) + %3 = extractvalue { i8, i1 } %2, 1 + ret i1 %3 + +; Multiply, return if the high byte is zero +; +; CHECK: mul r{{[0-9]+}}, r{{[0-9]+}} +; CHECK: mov [[HIGH:r[0-9]+]], r1 +; CHECK: ldi [[RET:r[0-9]+]], 1 +; CHECK: cpi {{.*}}[[HIGH]], 0 +; CHECK: brne [[LABEL:LBB[_0-9]+]] +; CHECK: ldi {{.*}}[[RET]], 0 +; CHECK: {{.*}}[[LABEL]] +; CHECK: ret +} + +declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8) |
