[AVR] Expand MULHS for all types

Once MULHS was expanded, this exposed an issue where the condition
register was thought to be 16-bit. This caused an attempt to copy a
16-bit register to an 8-bit register.

Authored by Jake Goulding

llvm-svn: 283634

3 files changed, 56 insertions, 0 deletions

diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h
index 2c8c9c88b6d..69aaaf2db21 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.h
+++ b/llvm/lib/Target/AVR/AVRISelLowering.h
@@ -92,6 +92,9 @@ public:
 
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
+  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+                         EVT VT) const override;
+
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *MBB) const override;
diff --git a/llvm/test/CodeGen/AVR/smul-with-overflow.ll b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
new file mode 100644
index 00000000000..745e93005cc
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+define i1 @signed_multiplication_did_overflow(i8, i8) unnamed_addr {
+; CHECK-LABEL: signed_multiplication_did_overflow:
+entry-block:
+  %2 = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %0, i8 %1)
+  %3 = extractvalue { i8, i1 } %2, 1
+  ret i1 %3
+
+; Multiply, fill the low byte with the sign of the low byte via
+; arithmetic shifting, compare it to the high byte.
+;
+; CHECK: muls   r24, r22
+; CHECK: mov    [[HIGH:r[0-9]+]], r1
+; CHECK: mov    [[LOW:r[0-9]+]], r0
+; CHECK: asr    {{.*}}[[LOW]]
+; CHECK: asr    {{.*}}[[LOW]]
+; CHECK: asr    {{.*}}[[LOW]]
+; CHECK: asr    {{.*}}[[LOW]]
+; CHECK: asr    {{.*}}[[LOW]]
+; CHECK: asr    {{.*}}[[LOW]]
+; CHECK: asr    {{.*}}[[LOW]]
+; CHECK: ldi    [[RET:r[0-9]+]], 1
+; CHECK: cp     {{.*}}[[HIGH]], {{.*}}[[LOW]]
+; CHECK: brne   [[LABEL:LBB[_0-9]+]]
+; CHECK: ldi    {{.*}}[[RET]], 0
+; CHECK: {{.*}}[[LABEL]]
+; CHECK: ret
+}
+
+declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8)
diff --git a/llvm/test/CodeGen/AVR/umul-with-overflow.ll b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
new file mode 100644
index 00000000000..aa8b10a313d
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=avr | FileCheck %s
+
+define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr {
+; CHECK-LABEL: unsigned_multiplication_did_overflow:
+entry-block:
+  %2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1)
+  %3 = extractvalue { i8, i1 } %2, 1
+  ret i1 %3
+
+; Multiply, return if the high byte is zero
+;
+; CHECK: mul    r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK: mov    [[HIGH:r[0-9]+]], r1
+; CHECK: ldi    [[RET:r[0-9]+]], 1
+; CHECK: cpi    {{.*}}[[HIGH]], 0
+; CHECK: brne   [[LABEL:LBB[_0-9]+]]
+; CHECK: ldi    {{.*}}[[RET]], 0
+; CHECK: {{.*}}[[LABEL]]
+; CHECK: ret
+}
+
+declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8)