[Codegen] Adjust saturation test. NFC.

Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be.

llvm-svn: 375009

8 files changed, 1327 insertions, 12 deletions

diff --git a/llvm/test/CodeGen/ARM/sadd_sat.ll b/llvm/test/CodeGen/ARM/sadd_sat.ll
index 387850c831f..e3d329c6a9d 100644
--- a/llvm/test/CodeGen/ARM/sadd_sat.ll
+++ b/llvm/test/CodeGen/ARM/sadd_sat.ll
@@ -207,7 +207,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
   ret i64 %tmp
 }
 
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
 ; CHECK-T1-LABEL: func16:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r3, r1, #16
@@ -276,7 +276,7 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
   ret i16 %tmp
 }
 
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
 ; CHECK-T1-LABEL: func8:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r3, r1, #24
@@ -345,7 +345,7 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
   ret i8 %tmp
 }
 
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
 ; CHECK-T1-LABEL: func3:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r3, r1, #28
diff --git a/llvm/test/CodeGen/ARM/sadd_sat_plus.ll b/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
new file mode 100644
index 00000000000..8d41eb6685d
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
@@ -0,0 +1,433 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.sadd.sat.i4(i4, i4)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    mov r3, r0
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    movs r2, #1
+; CHECK-T1-NEXT:    adds r0, r0, r1
+; CHECK-T1-NEXT:    mov r1, r2
+; CHECK-T1-NEXT:    bmi .LBB0_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r1, #0
+; CHECK-T1-NEXT:  .LBB0_2:
+; CHECK-T1-NEXT:    cmp r1, #0
+; CHECK-T1-NEXT:    bne .LBB0_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r1, r2, #31
+; CHECK-T1-NEXT:    cmp r0, r3
+; CHECK-T1-NEXT:    bvs .LBB0_5
+; CHECK-T1-NEXT:    b .LBB0_6
+; CHECK-T1-NEXT:  .LBB0_4:
+; CHECK-T1-NEXT:    ldr r1, .LCPI0_0
+; CHECK-T1-NEXT:    cmp r0, r3
+; CHECK-T1-NEXT:    bvc .LBB0_6
+; CHECK-T1-NEXT:  .LBB0_5:
+; CHECK-T1-NEXT:    mov r0, r1
+; CHECK-T1-NEXT:  .LBB0_6:
+; CHECK-T1-NEXT:    bx lr
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI0_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    mla r2, r1, r2, r0
+; CHECK-T2-NEXT:    movs r3, #0
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r3, #1
+; CHECK-T2-NEXT:    cmp r3, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r1, #-2147483648
+; CHECK-T2-NEXT:    cmp r2, r0
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r1, r2
+; CHECK-T2-NEXT:    mov r0, r1
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mla r2, r1, r2, r0
+; CHECK-ARM-NEXT:    mov r3, #0
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    movwmi r3, #1
+; CHECK-ARM-NEXT:    cmp r3, #0
+; CHECK-ARM-NEXT:    mvnne r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r2, r0
+; CHECK-ARM-NEXT:    movvc r1, r2
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i32 %y, %z
+  %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
+  ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT:    push {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT:    .pad #4
+; CHECK-T1-NEXT:    sub sp, #4
+; CHECK-T1-NEXT:    ldr r5, [sp, #28]
+; CHECK-T1-NEXT:    movs r2, #1
+; CHECK-T1-NEXT:    movs r4, #0
+; CHECK-T1-NEXT:    cmp r5, #0
+; CHECK-T1-NEXT:    mov r3, r2
+; CHECK-T1-NEXT:    bge .LBB1_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    mov r3, r4
+; CHECK-T1-NEXT:  .LBB1_2:
+; CHECK-T1-NEXT:    cmp r1, #0
+; CHECK-T1-NEXT:    mov r6, r2
+; CHECK-T1-NEXT:    bge .LBB1_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    mov r6, r4
+; CHECK-T1-NEXT:  .LBB1_4:
+; CHECK-T1-NEXT:    subs r7, r6, r3
+; CHECK-T1-NEXT:    rsbs r3, r7, #0
+; CHECK-T1-NEXT:    adcs r3, r7
+; CHECK-T1-NEXT:    ldr r7, [sp, #24]
+; CHECK-T1-NEXT:    adds r0, r0, r7
+; CHECK-T1-NEXT:    adcs r1, r5
+; CHECK-T1-NEXT:    cmp r1, #0
+; CHECK-T1-NEXT:    mov r5, r2
+; CHECK-T1-NEXT:    bge .LBB1_6
+; CHECK-T1-NEXT:  @ %bb.5:
+; CHECK-T1-NEXT:    mov r5, r4
+; CHECK-T1-NEXT:  .LBB1_6:
+; CHECK-T1-NEXT:    subs r4, r6, r5
+; CHECK-T1-NEXT:    subs r5, r4, #1
+; CHECK-T1-NEXT:    sbcs r4, r5
+; CHECK-T1-NEXT:    ands r3, r4
+; CHECK-T1-NEXT:    beq .LBB1_8
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:    asrs r0, r1, #31
+; CHECK-T1-NEXT:  .LBB1_8:
+; CHECK-T1-NEXT:    cmp r1, #0
+; CHECK-T1-NEXT:    bmi .LBB1_10
+; CHECK-T1-NEXT:  @ %bb.9:
+; CHECK-T1-NEXT:    lsls r2, r2, #31
+; CHECK-T1-NEXT:    cmp r3, #0
+; CHECK-T1-NEXT:    beq .LBB1_11
+; CHECK-T1-NEXT:    b .LBB1_12
+; CHECK-T1-NEXT:  .LBB1_10:
+; CHECK-T1-NEXT:    ldr r2, .LCPI1_0
+; CHECK-T1-NEXT:    cmp r3, #0
+; CHECK-T1-NEXT:    bne .LBB1_12
+; CHECK-T1-NEXT:  .LBB1_11:
+; CHECK-T1-NEXT:    mov r2, r1
+; CHECK-T1-NEXT:  .LBB1_12:
+; CHECK-T1-NEXT:    mov r1, r2
+; CHECK-T1-NEXT:    add sp, #4
+; CHECK-T1-NEXT:    pop {r4, r5, r6, r7, pc}
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.13:
+; CHECK-T1-NEXT:  .LCPI1_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    .save {r7, lr}
+; CHECK-T2-NEXT:    push {r7, lr}
+; CHECK-T2-NEXT:    ldrd r2, r12, [sp, #8]
+; CHECK-T2-NEXT:    cmp.w r1, #-1
+; CHECK-T2-NEXT:    mov.w r3, #0
+; CHECK-T2-NEXT:    mov.w lr, #0
+; CHECK-T2-NEXT:    it gt
+; CHECK-T2-NEXT:    movgt r3, #1
+; CHECK-T2-NEXT:    adds r0, r0, r2
+; CHECK-T2-NEXT:    adc.w r2, r1, r12
+; CHECK-T2-NEXT:    movs r1, #0
+; CHECK-T2-NEXT:    cmp.w r2, #-1
+; CHECK-T2-NEXT:    it gt
+; CHECK-T2-NEXT:    movgt r1, #1
+; CHECK-T2-NEXT:    subs r1, r3, r1
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    movne r1, #1
+; CHECK-T2-NEXT:    cmp.w r12, #-1
+; CHECK-T2-NEXT:    it gt
+; CHECK-T2-NEXT:    movgt.w lr, #1
+; CHECK-T2-NEXT:    sub.w r3, r3, lr
+; CHECK-T2-NEXT:    clz r3, r3
+; CHECK-T2-NEXT:    lsrs r3, r3, #5
+; CHECK-T2-NEXT:    ands r3, r1
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    asrne r0, r2, #31
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    mvnmi r1, #-2147483648
+; CHECK-T2-NEXT:    cmp r3, #0
+; CHECK-T2-NEXT:    it eq
+; CHECK-T2-NEXT:    moveq r1, r2
+; CHECK-T2-NEXT:    pop {r7, pc}
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    .save {r11, lr}
+; CHECK-ARM-NEXT:    push {r11, lr}
+; CHECK-ARM-NEXT:    ldr r2, [sp, #8]
+; CHECK-ARM-NEXT:    mov r3, #0
+; CHECK-ARM-NEXT:    ldr r12, [sp, #12]
+; CHECK-ARM-NEXT:    adds r0, r0, r2
+; CHECK-ARM-NEXT:    mov r2, #0
+; CHECK-ARM-NEXT:    adc lr, r1, r12
+; CHECK-ARM-NEXT:    cmn r1, #1
+; CHECK-ARM-NEXT:    mov r1, #0
+; CHECK-ARM-NEXT:    movwgt r1, #1
+; CHECK-ARM-NEXT:    cmn lr, #1
+; CHECK-ARM-NEXT:    movwgt r2, #1
+; CHECK-ARM-NEXT:    subs r2, r1, r2
+; CHECK-ARM-NEXT:    movwne r2, #1
+; CHECK-ARM-NEXT:    cmn r12, #1
+; CHECK-ARM-NEXT:    movwgt r3, #1
+; CHECK-ARM-NEXT:    sub r1, r1, r3
+; CHECK-ARM-NEXT:    clz r1, r1
+; CHECK-ARM-NEXT:    lsr r1, r1, #5
+; CHECK-ARM-NEXT:    ands r2, r1, r2
+; CHECK-ARM-NEXT:    asrne r0, lr, #31
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp lr, #0
+; CHECK-ARM-NEXT:    mvnmi r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    moveq r1, lr
+; CHECK-ARM-NEXT:    pop {r11, pc}
+  %a = mul i64 %y, %z
+  %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
+  ret i64 %tmp
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r3, r1, #16
+; CHECK-T1-NEXT:    lsls r1, r0, #16
+; CHECK-T1-NEXT:    movs r2, #1
+; CHECK-T1-NEXT:    adds r0, r1, r3
+; CHECK-T1-NEXT:    mov r3, r2
+; CHECK-T1-NEXT:    bmi .LBB2_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r3, #0
+; CHECK-T1-NEXT:  .LBB2_2:
+; CHECK-T1-NEXT:    cmp r3, #0
+; CHECK-T1-NEXT:    bne .LBB2_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r2, r2, #31
+; CHECK-T1-NEXT:    cmp r0, r1
+; CHECK-T1-NEXT:    bvs .LBB2_5
+; CHECK-T1-NEXT:    b .LBB2_6
+; CHECK-T1-NEXT:  .LBB2_4:
+; CHECK-T1-NEXT:    ldr r2, .LCPI2_0
+; CHECK-T1-NEXT:    cmp r0, r1
+; CHECK-T1-NEXT:    bvc .LBB2_6
+; CHECK-T1-NEXT:  .LBB2_5:
+; CHECK-T1-NEXT:    mov r0, r2
+; CHECK-T1-NEXT:  .LBB2_6:
+; CHECK-T1-NEXT:    asrs r0, r0, #16
+; CHECK-T1-NEXT:    bx lr
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI2_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r2, r0, #16
+; CHECK-T2-NEXT:    mov.w r3, #-2147483648
+; CHECK-T2-NEXT:    add.w r1, r2, r1, lsl #16
+; CHECK-T2-NEXT:    movs r2, #0
+; CHECK-T2-NEXT:    cmp r1, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r2, #1
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r3, #-2147483648
+; CHECK-T2-NEXT:    cmp.w r1, r0, lsl #16
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r3, r1
+; CHECK-T2-NEXT:    asrs r0, r3, #16
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r2, r0, #16
+; CHECK-ARM-NEXT:    mov r3, #-2147483648
+; CHECK-ARM-NEXT:    add r1, r2, r1, lsl #16
+; CHECK-ARM-NEXT:    mov r2, #0
+; CHECK-ARM-NEXT:    cmp r1, #0
+; CHECK-ARM-NEXT:    movwmi r2, #1
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    mvnne r3, #-2147483648
+; CHECK-ARM-NEXT:    cmp r1, r0, lsl #16
+; CHECK-ARM-NEXT:    movvc r3, r1
+; CHECK-ARM-NEXT:    asr r0, r3, #16
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i16 %y, %z
+  %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
+  ret i16 %tmp
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r3, r1, #24
+; CHECK-T1-NEXT:    lsls r1, r0, #24
+; CHECK-T1-NEXT:    movs r2, #1
+; CHECK-T1-NEXT:    adds r0, r1, r3
+; CHECK-T1-NEXT:    mov r3, r2
+; CHECK-T1-NEXT:    bmi .LBB3_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r3, #0
+; CHECK-T1-NEXT:  .LBB3_2:
+; CHECK-T1-NEXT:    cmp r3, #0
+; CHECK-T1-NEXT:    bne .LBB3_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r2, r2, #31
+; CHECK-T1-NEXT:    cmp r0, r1
+; CHECK-T1-NEXT:    bvs .LBB3_5
+; CHECK-T1-NEXT:    b .LBB3_6
+; CHECK-T1-NEXT:  .LBB3_4:
+; CHECK-T1-NEXT:    ldr r2, .LCPI3_0
+; CHECK-T1-NEXT:    cmp r0, r1
+; CHECK-T1-NEXT:    bvc .LBB3_6
+; CHECK-T1-NEXT:  .LBB3_5:
+; CHECK-T1-NEXT:    mov r0, r2
+; CHECK-T1-NEXT:  .LBB3_6:
+; CHECK-T1-NEXT:    asrs r0, r0, #24
+; CHECK-T1-NEXT:    bx lr
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI3_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r2, r0, #24
+; CHECK-T2-NEXT:    mov.w r3, #-2147483648
+; CHECK-T2-NEXT:    add.w r1, r2, r1, lsl #24
+; CHECK-T2-NEXT:    movs r2, #0
+; CHECK-T2-NEXT:    cmp r1, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r2, #1
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r3, #-2147483648
+; CHECK-T2-NEXT:    cmp.w r1, r0, lsl #24
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r3, r1
+; CHECK-T2-NEXT:    asrs r0, r3, #24
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r2, r0, #24
+; CHECK-ARM-NEXT:    mov r3, #-2147483648
+; CHECK-ARM-NEXT:    add r1, r2, r1, lsl #24
+; CHECK-ARM-NEXT:    mov r2, #0
+; CHECK-ARM-NEXT:    cmp r1, #0
+; CHECK-ARM-NEXT:    movwmi r2, #1
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    mvnne r3, #-2147483648
+; CHECK-ARM-NEXT:    cmp r1, r0, lsl #24
+; CHECK-ARM-NEXT:    movvc r3, r1
+; CHECK-ARM-NEXT:    asr r0, r3, #24
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i8 %y, %z
+  %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
+  ret i8 %tmp
+}
+
+define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r3, r1, #28
+; CHECK-T1-NEXT:    lsls r1, r0, #28
+; CHECK-T1-NEXT:    movs r2, #1
+; CHECK-T1-NEXT:    adds r0, r1, r3
+; CHECK-T1-NEXT:    mov r3, r2
+; CHECK-T1-NEXT:    bmi .LBB4_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r3, #0
+; CHECK-T1-NEXT:  .LBB4_2:
+; CHECK-T1-NEXT:    cmp r3, #0
+; CHECK-T1-NEXT:    bne .LBB4_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r2, r2, #31
+; CHECK-T1-NEXT:    cmp r0, r1
+; CHECK-T1-NEXT:    bvs .LBB4_5
+; CHECK-T1-NEXT:    b .LBB4_6
+; CHECK-T1-NEXT:  .LBB4_4:
+; CHECK-T1-NEXT:    ldr r2, .LCPI4_0
+; CHECK-T1-NEXT:    cmp r0, r1
+; CHECK-T1-NEXT:    bvc .LBB4_6
+; CHECK-T1-NEXT:  .LBB4_5:
+; CHECK-T1-NEXT:    mov r0, r2
+; CHECK-T1-NEXT:  .LBB4_6:
+; CHECK-T1-NEXT:    asrs r0, r0, #28
+; CHECK-T1-NEXT:    bx lr
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI4_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r2, r0, #28
+; CHECK-T2-NEXT:    mov.w r3, #-2147483648
+; CHECK-T2-NEXT:    add.w r1, r2, r1, lsl #28
+; CHECK-T2-NEXT:    movs r2, #0
+; CHECK-T2-NEXT:    cmp r1, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r2, #1
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r3, #-2147483648
+; CHECK-T2-NEXT:    cmp.w r1, r0, lsl #28
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r3, r1
+; CHECK-T2-NEXT:    asrs r0, r3, #28
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r2, r0, #28
+; CHECK-ARM-NEXT:    mov r3, #-2147483648
+; CHECK-ARM-NEXT:    add r1, r2, r1, lsl #28
+; CHECK-ARM-NEXT:    mov r2, #0
+; CHECK-ARM-NEXT:    cmp r1, #0
+; CHECK-ARM-NEXT:    movwmi r2, #1
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    mvnne r3, #-2147483648
+; CHECK-ARM-NEXT:    cmp r1, r0, lsl #28
+; CHECK-ARM-NEXT:    movvc r3, r1
+; CHECK-ARM-NEXT:    asr r0, r3, #28
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i4 %y, %z
+  %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
+  ret i4 %tmp
+}
diff --git a/llvm/test/CodeGen/ARM/ssub_sat.ll b/llvm/test/CodeGen/ARM/ssub_sat.ll
index b31dc0f1686..c6305cec4d3 100644
--- a/llvm/test/CodeGen/ARM/ssub_sat.ll
+++ b/llvm/test/CodeGen/ARM/ssub_sat.ll
@@ -209,7 +209,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
   ret i64 %tmp
 }
 
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
 ; CHECK-T1-LABEL: func16:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    .save {r4, lr}
@@ -280,7 +280,7 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
   ret i16 %tmp
 }
 
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
 ; CHECK-T1-LABEL: func8:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    .save {r4, lr}
@@ -351,7 +351,7 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
   ret i8 %tmp
 }
 
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
 ; CHECK-T1-LABEL: func3:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    .save {r4, lr}
diff --git a/llvm/test/CodeGen/ARM/ssub_sat_plus.ll b/llvm/test/CodeGen/ARM/ssub_sat_plus.ll
new file mode 100644
index 00000000000..67c655391d1
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ssub_sat_plus.ll
@@ -0,0 +1,445 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.ssub.sat.i4(i4, i4)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, lr}
+; CHECK-T1-NEXT:    push {r4, lr}
+; CHECK-T1-NEXT:    mov r3, r0
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    movs r2, #1
+; CHECK-T1-NEXT:    subs r0, r0, r1
+; CHECK-T1-NEXT:    mov r4, r2
+; CHECK-T1-NEXT:    bmi .LBB0_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r4, #0
+; CHECK-T1-NEXT:  .LBB0_2:
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    bne .LBB0_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r2, r2, #31
+; CHECK-T1-NEXT:    cmp r3, r1
+; CHECK-T1-NEXT:    bvs .LBB0_5
+; CHECK-T1-NEXT:    b .LBB0_6
+; CHECK-T1-NEXT:  .LBB0_4:
+; CHECK-T1-NEXT:    ldr r2, .LCPI0_0
+; CHECK-T1-NEXT:    cmp r3, r1
+; CHECK-T1-NEXT:    bvc .LBB0_6
+; CHECK-T1-NEXT:  .LBB0_5:
+; CHECK-T1-NEXT:    mov r0, r2
+; CHECK-T1-NEXT:  .LBB0_6:
+; CHECK-T1-NEXT:    pop {r4, pc}
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI0_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    .save {r7, lr}
+; CHECK-T2-NEXT:    push {r7, lr}
+; CHECK-T2-NEXT:    mls r12, r1, r2, r0
+; CHECK-T2-NEXT:    mov.w lr, #0
+; CHECK-T2-NEXT:    mov.w r3, #-2147483648
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    cmp.w r12, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi.w lr, #1
+; CHECK-T2-NEXT:    cmp.w lr, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r3, #-2147483648
+; CHECK-T2-NEXT:    cmp r0, r1
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r3, r12
+; CHECK-T2-NEXT:    mov r0, r3
+; CHECK-T2-NEXT:    pop {r7, pc}
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mls r3, r1, r2, r0
+; CHECK-ARM-NEXT:    mul r12, r1, r2
+; CHECK-ARM-NEXT:    mov r2, #0
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r3, #0
+; CHECK-ARM-NEXT:    movwmi r2, #1
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    mvnne r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r0, r12
+; CHECK-ARM-NEXT:    movvc r1, r3
+; CHECK-ARM-NEXT:    mov r0, r1
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i32 %y, %z
+  %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
+  ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT:    push {r4, r5, r6, r7, lr}
+; CHECK-T1-NEXT:    .pad #4
+; CHECK-T1-NEXT:    sub sp, #4
+; CHECK-T1-NEXT:    ldr r5, [sp, #28]
+; CHECK-T1-NEXT:    movs r2, #1
+; CHECK-T1-NEXT:    movs r4, #0
+; CHECK-T1-NEXT:    cmp r5, #0
+; CHECK-T1-NEXT:    mov r3, r2
+; CHECK-T1-NEXT:    bge .LBB1_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    mov r3, r4
+; CHECK-T1-NEXT:  .LBB1_2:
+; CHECK-T1-NEXT:    cmp r1, #0
+; CHECK-T1-NEXT:    mov r6, r2
+; CHECK-T1-NEXT:    bge .LBB1_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    mov r6, r4
+; CHECK-T1-NEXT:  .LBB1_4:
+; CHECK-T1-NEXT:    subs r3, r6, r3
+; CHECK-T1-NEXT:    subs r7, r3, #1
+; CHECK-T1-NEXT:    sbcs r3, r7
+; CHECK-T1-NEXT:    ldr r7, [sp, #24]
+; CHECK-T1-NEXT:    subs r0, r0, r7
+; CHECK-T1-NEXT:    sbcs r1, r5
+; CHECK-T1-NEXT:    cmp r1, #0
+; CHECK-T1-NEXT:    mov r5, r2
+; CHECK-T1-NEXT:    bge .LBB1_6
+; CHECK-T1-NEXT:  @ %bb.5:
+; CHECK-T1-NEXT:    mov r5, r4
+; CHECK-T1-NEXT:  .LBB1_6:
+; CHECK-T1-NEXT:    subs r4, r6, r5
+; CHECK-T1-NEXT:    subs r5, r4, #1
+; CHECK-T1-NEXT:    sbcs r4, r5
+; CHECK-T1-NEXT:    ands r3, r4
+; CHECK-T1-NEXT:    beq .LBB1_8
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:    asrs r0, r1, #31
+; CHECK-T1-NEXT:  .LBB1_8:
+; CHECK-T1-NEXT:    cmp r1, #0
+; CHECK-T1-NEXT:    bmi .LBB1_10
+; CHECK-T1-NEXT:  @ %bb.9:
+; CHECK-T1-NEXT:    lsls r2, r2, #31
+; CHECK-T1-NEXT:    cmp r3, #0
+; CHECK-T1-NEXT:    beq .LBB1_11
+; CHECK-T1-NEXT:    b .LBB1_12
+; CHECK-T1-NEXT:  .LBB1_10:
+; CHECK-T1-NEXT:    ldr r2, .LCPI1_0
+; CHECK-T1-NEXT:    cmp r3, #0
+; CHECK-T1-NEXT:    bne .LBB1_12
+; CHECK-T1-NEXT:  .LBB1_11:
+; CHECK-T1-NEXT:    mov r2, r1
+; CHECK-T1-NEXT:  .LBB1_12:
+; CHECK-T1-NEXT:    mov r1, r2
+; CHECK-T1-NEXT:    add sp, #4
+; CHECK-T1-NEXT:    pop {r4, r5, r6, r7, pc}
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.13:
+; CHECK-T1-NEXT:  .LCPI1_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    .save {r4, lr}
+; CHECK-T2-NEXT:    push {r4, lr}
+; CHECK-T2-NEXT:    ldr.w r12, [sp, #12]
+; CHECK-T2-NEXT:    movs r2, #0
+; CHECK-T2-NEXT:    movs r3, #0
+; CHECK-T2-NEXT:    ldr r4, [sp, #8]
+; CHECK-T2-NEXT:    cmp.w r12, #-1
+; CHECK-T2-NEXT:    it gt
+; CHECK-T2-NEXT:    movgt r2, #1
+; CHECK-T2-NEXT:    cmp.w r1, #-1
+; CHECK-T2-NEXT:    it gt
+; CHECK-T2-NEXT:    movgt r3, #1
+; CHECK-T2-NEXT:    subs r2, r3, r2
+; CHECK-T2-NEXT:    mov.w lr, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    movne r2, #1
+; CHECK-T2-NEXT:    subs r0, r0, r4
+; CHECK-T2-NEXT:    sbc.w r4, r1, r12
+; CHECK-T2-NEXT:    cmp.w r4, #-1
+; CHECK-T2-NEXT:    it gt
+; CHECK-T2-NEXT:    movgt.w lr, #1
+; CHECK-T2-NEXT:    subs.w r1, r3, lr
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    movne r1, #1
+; CHECK-T2-NEXT:    ands r2, r1
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    asrne r0, r4, #31
+; CHECK-T2-NEXT:    cmp r4, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    mvnmi r1, #-2147483648
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it eq
+; CHECK-T2-NEXT:    moveq r1, r4
+; CHECK-T2-NEXT:    pop {r4, pc}
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    .save {r4, r5, r11, lr}
+; CHECK-ARM-NEXT:    push {r4, r5, r11, lr}
+; CHECK-ARM-NEXT:    ldr lr, [sp, #20]
+; CHECK-ARM-NEXT:    cmn r1, #1
+; CHECK-ARM-NEXT:    mov r3, #0
+; CHECK-ARM-NEXT:    mov r4, #0
+; CHECK-ARM-NEXT:    movwgt r3, #1
+; CHECK-ARM-NEXT:    cmn lr, #1
+; CHECK-ARM-NEXT:    movwgt r4, #1
+; CHECK-ARM-NEXT:    ldr r12, [sp, #16]
+; CHECK-ARM-NEXT:    subs r4, r3, r4
+; CHECK-ARM-NEXT:    mov r5, #0
+; CHECK-ARM-NEXT:    movwne r4, #1
+; CHECK-ARM-NEXT:    subs r0, r0, r12
+; CHECK-ARM-NEXT:    sbc r2, r1, lr
+; CHECK-ARM-NEXT:    cmn r2, #1
+; CHECK-ARM-NEXT:    movwgt r5, #1
+; CHECK-ARM-NEXT:    subs r1, r3, r5
+; CHECK-ARM-NEXT:    movwne r1, #1
+; CHECK-ARM-NEXT:    ands r3, r4, r1
+; CHECK-ARM-NEXT:    asrne r0, r2, #31
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    mvnmi r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r3, #0
+; CHECK-ARM-NEXT:    moveq r1, r2
+; CHECK-ARM-NEXT:    pop {r4, r5, r11, pc}
+  %a = mul i64 %y, %z
+  %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
+  ret i64 %tmp
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, lr}
+; CHECK-T1-NEXT:    push {r4, lr}
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #16
+; CHECK-T1-NEXT:    lsls r2, r0, #16
+; CHECK-T1-NEXT:    movs r3, #1
+; CHECK-T1-NEXT:    subs r0, r2, r1
+; CHECK-T1-NEXT:    mov r4, r3
+; CHECK-T1-NEXT:    bmi .LBB2_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r4, #0
+; CHECK-T1-NEXT:  .LBB2_2:
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    bne .LBB2_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r3, r3, #31
+; CHECK-T1-NEXT:    cmp r2, r1
+; CHECK-T1-NEXT:    bvs .LBB2_5
+; CHECK-T1-NEXT:    b .LBB2_6
+; CHECK-T1-NEXT:  .LBB2_4:
+; CHECK-T1-NEXT:    ldr r3, .LCPI2_0
+; CHECK-T1-NEXT:    cmp r2, r1
+; CHECK-T1-NEXT:    bvc .LBB2_6
+; CHECK-T1-NEXT:  .LBB2_5:
+; CHECK-T1-NEXT:    mov r0, r3
+; CHECK-T1-NEXT:  .LBB2_6:
+; CHECK-T1-NEXT:    asrs r0, r0, #16
+; CHECK-T1-NEXT:    pop {r4, pc}
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI2_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    mul r12, r1, r2
+; CHECK-T2-NEXT:    lsls r0, r0, #16
+; CHECK-T2-NEXT:    movs r3, #0
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
+; CHECK-T2-NEXT:    sub.w r2, r0, r12, lsl #16
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r3, #1
+; CHECK-T2-NEXT:    cmp r3, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r1, #-2147483648
+; CHECK-T2-NEXT:    cmp.w r0, r12, lsl #16
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r1, r2
+; CHECK-T2-NEXT:    asrs r0, r1, #16
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r12, r1, r2
+; CHECK-ARM-NEXT:    lsl r0, r0, #16
+; CHECK-ARM-NEXT:    mov r3, #0
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    sub r2, r0, r12, lsl #16
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    movwmi r3, #1
+; CHECK-ARM-NEXT:    cmp r3, #0
+; CHECK-ARM-NEXT:    mvnne r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r0, r12, lsl #16
+; CHECK-ARM-NEXT:    movvc r1, r2
+; CHECK-ARM-NEXT:    asr r0, r1, #16
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i16 %y, %z
+  %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
+  ret i16 %tmp
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, lr}
+; CHECK-T1-NEXT:    push {r4, lr}
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #24
+; CHECK-T1-NEXT:    lsls r2, r0, #24
+; CHECK-T1-NEXT:    movs r3, #1
+; CHECK-T1-NEXT:    subs r0, r2, r1
+; CHECK-T1-NEXT:    mov r4, r3
+; CHECK-T1-NEXT:    bmi .LBB3_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r4, #0
+; CHECK-T1-NEXT:  .LBB3_2:
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    bne .LBB3_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r3, r3, #31
+; CHECK-T1-NEXT:    cmp r2, r1
+; CHECK-T1-NEXT:    bvs .LBB3_5
+; CHECK-T1-NEXT:    b .LBB3_6
+; CHECK-T1-NEXT:  .LBB3_4:
+; CHECK-T1-NEXT:    ldr r3, .LCPI3_0
+; CHECK-T1-NEXT:    cmp r2, r1
+; CHECK-T1-NEXT:    bvc .LBB3_6
+; CHECK-T1-NEXT:  .LBB3_5:
+; CHECK-T1-NEXT:    mov r0, r3
+; CHECK-T1-NEXT:  .LBB3_6:
+; CHECK-T1-NEXT:    asrs r0, r0, #24
+; CHECK-T1-NEXT:    pop {r4, pc}
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI3_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    mul r12, r1, r2
+; CHECK-T2-NEXT:    lsls r0, r0, #24
+; CHECK-T2-NEXT:    movs r3, #0
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
+; CHECK-T2-NEXT:    sub.w r2, r0, r12, lsl #24
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r3, #1
+; CHECK-T2-NEXT:    cmp r3, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r1, #-2147483648
+; CHECK-T2-NEXT:    cmp.w r0, r12, lsl #24
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r1, r2
+; CHECK-T2-NEXT:    asrs r0, r1, #24
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r12, r1, r2
+; CHECK-ARM-NEXT:    lsl r0, r0, #24
+; CHECK-ARM-NEXT:    mov r3, #0
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    sub r2, r0, r12, lsl #24
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    movwmi r3, #1
+; CHECK-ARM-NEXT:    cmp r3, #0
+; CHECK-ARM-NEXT:    mvnne r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r0, r12, lsl #24
+; CHECK-ARM-NEXT:    movvc r1, r2
+; CHECK-ARM-NEXT:    asr r0, r1, #24
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i8 %y, %z
+  %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
+  ret i8 %tmp
+}
+
+define signext i4 @func4(i4 signext %x, i4 signext %y, i4 signext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, lr}
+; CHECK-T1-NEXT:    push {r4, lr}
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #28
+; CHECK-T1-NEXT:    lsls r2, r0, #28
+; CHECK-T1-NEXT:    movs r3, #1
+; CHECK-T1-NEXT:    subs r0, r2, r1
+; CHECK-T1-NEXT:    mov r4, r3
+; CHECK-T1-NEXT:    bmi .LBB4_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r4, #0
+; CHECK-T1-NEXT:  .LBB4_2:
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    bne .LBB4_4
+; CHECK-T1-NEXT:  @ %bb.3:
+; CHECK-T1-NEXT:    lsls r3, r3, #31
+; CHECK-T1-NEXT:    cmp r2, r1
+; CHECK-T1-NEXT:    bvs .LBB4_5
+; CHECK-T1-NEXT:    b .LBB4_6
+; CHECK-T1-NEXT:  .LBB4_4:
+; CHECK-T1-NEXT:    ldr r3, .LCPI4_0
+; CHECK-T1-NEXT:    cmp r2, r1
+; CHECK-T1-NEXT:    bvc .LBB4_6
+; CHECK-T1-NEXT:  .LBB4_5:
+; CHECK-T1-NEXT:    mov r0, r3
+; CHECK-T1-NEXT:  .LBB4_6:
+; CHECK-T1-NEXT:    asrs r0, r0, #28
+; CHECK-T1-NEXT:    pop {r4, pc}
+; CHECK-T1-NEXT:    .p2align 2
+; CHECK-T1-NEXT:  @ %bb.7:
+; CHECK-T1-NEXT:  .LCPI4_0:
+; CHECK-T1-NEXT:    .long 2147483647 @ 0x7fffffff
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    mul r12, r1, r2
+; CHECK-T2-NEXT:    lsls r0, r0, #28
+; CHECK-T2-NEXT:    movs r3, #0
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
+; CHECK-T2-NEXT:    sub.w r2, r0, r12, lsl #28
+; CHECK-T2-NEXT:    cmp r2, #0
+; CHECK-T2-NEXT:    it mi
+; CHECK-T2-NEXT:    movmi r3, #1
+; CHECK-T2-NEXT:    cmp r3, #0
+; CHECK-T2-NEXT:    it ne
+; CHECK-T2-NEXT:    mvnne r1, #-2147483648
+; CHECK-T2-NEXT:    cmp.w r0, r12, lsl #28
+; CHECK-T2-NEXT:    it vc
+; CHECK-T2-NEXT:    movvc r1, r2
+; CHECK-T2-NEXT:    asrs r0, r1, #28
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r12, r1, r2
+; CHECK-ARM-NEXT:    lsl r0, r0, #28
+; CHECK-ARM-NEXT:    mov r3, #0
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    sub r2, r0, r12, lsl #28
+; CHECK-ARM-NEXT:    cmp r2, #0
+; CHECK-ARM-NEXT:    movwmi r3, #1
+; CHECK-ARM-NEXT:    cmp r3, #0
+; CHECK-ARM-NEXT:    mvnne r1, #-2147483648
+; CHECK-ARM-NEXT:    cmp r0, r12, lsl #28
+; CHECK-ARM-NEXT:    movvc r1, r2
+; CHECK-ARM-NEXT:    asr r0, r1, #28
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i4 %y, %z
+  %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a)
+  ret i4 %tmp
+}
diff --git a/llvm/test/CodeGen/ARM/uadd_sat.ll b/llvm/test/CodeGen/ARM/uadd_sat.ll
index 2843f85af51..3de65959156 100644
--- a/llvm/test/CodeGen/ARM/uadd_sat.ll
+++ b/llvm/test/CodeGen/ARM/uadd_sat.ll
@@ -90,7 +90,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
   ret i64 %tmp
 }
 
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
 ; CHECK-T1-LABEL: func16:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r1, r1, #16
@@ -126,7 +126,7 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
   ret i16 %tmp
 }
 
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
 ; CHECK-T1-LABEL: func8:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r1, r1, #24
@@ -162,7 +162,7 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
   ret i8 %tmp
 }
 
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
 ; CHECK-T1-LABEL: func3:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r1, r1, #28
diff --git a/llvm/test/CodeGen/ARM/uadd_sat_plus.ll b/llvm/test/CodeGen/ARM/uadd_sat_plus.ll
new file mode 100644
index 00000000000..64f7c0d9ade
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/uadd_sat_plus.ll
@@ -0,0 +1,219 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.uadd.sat.i4(i4, i4)
+declare i8 @llvm.uadd.sat.i8(i8, i8)
+declare i16 @llvm.uadd.sat.i16(i16, i16)
+declare i32 @llvm.uadd.sat.i32(i32, i32)
+declare i64 @llvm.uadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    adds r0, r0, r1
+; CHECK-T1-NEXT:    blo .LBB0_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:    mvns r0, r0
+; CHECK-T1-NEXT:  .LBB0_2:
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    adds r0, r0, r1
+; CHECK-T2-NEXT:    it hs
+; CHECK-T2-NEXT:    movhs.w r0, #-1
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mul r1, r1, r2
+; CHECK-ARM-NEXT:    adds r0, r0, r1
+; CHECK-ARM-NEXT:    mvnhs r0, #0
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i32 %y, %z
+  %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)
+  ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, r5, r7, lr}
+; CHECK-T1-NEXT:    push {r4, r5, r7, lr}
+; CHECK-T1-NEXT:    movs r5, #0
+; CHECK-T1-NEXT:    ldr r2, [sp, #20]
+; CHECK-T1-NEXT:    ldr r3, [sp, #16]
+; CHECK-T1-NEXT:    adds r3, r0, r3
+; CHECK-T1-NEXT:    adcs r2, r1
+; CHECK-T1-NEXT:    mov r4, r5
+; CHECK-T1-NEXT:    adcs r4, r5
+; CHECK-T1-NEXT:    mvns r1, r5
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    mov r0, r1
+; CHECK-T1-NEXT:    beq .LBB1_3
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    beq .LBB1_4
+; CHECK-T1-NEXT:  .LBB1_2:
+; CHECK-T1-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-T1-NEXT:  .LBB1_3:
+; CHECK-T1-NEXT:    mov r0, r3
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    bne .LBB1_2
+; CHECK-T1-NEXT:  .LBB1_4:
+; CHECK-T1-NEXT:    mov r1, r2
+; CHECK-T1-NEXT:    pop {r4, r5, r7, pc}
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    ldrd r2, r3, [sp]
+; CHECK-T2-NEXT:    mov.w r12, #0
+; CHECK-T2-NEXT:    adds r0, r0, r2
+; CHECK-T2-NEXT:    adcs r1, r3
+; CHECK-T2-NEXT:    adcs r2, r12, #0
+; CHECK-T2-NEXT:    itt ne
+; CHECK-T2-NEXT:    movne.w r0, #-1
+; CHECK-T2-NEXT:    movne.w r1, #-1
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    ldr r2, [sp]
+; CHECK-ARM-NEXT:    mov r12, #0
+; CHECK-ARM-NEXT:    ldr r3, [sp, #4]
+; CHECK-ARM-NEXT:    adds r0, r0, r2
+; CHECK-ARM-NEXT:    adcs r1, r1, r3
+; CHECK-ARM-NEXT:    adcs r2, r12, #0
+; CHECK-ARM-NEXT:    mvnne r0, #0
+; CHECK-ARM-NEXT:    mvnne r1, #0
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i64 %y, %z
+  %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)
+  ret i64 %tmp
+}
+
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #16
+; CHECK-T1-NEXT:    lsls r0, r0, #16
+; CHECK-T1-NEXT:    adds r0, r0, r1
+; CHECK-T1-NEXT:    blo .LBB2_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:    mvns r0, r0
+; CHECK-T1-NEXT:  .LBB2_2:
+; CHECK-T1-NEXT:    lsrs r0, r0, #16
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r2, r0, #16
+; CHECK-T2-NEXT:    add.w r1, r2, r1, lsl #16
+; CHECK-T2-NEXT:    cmp.w r1, r0, lsl #16
+; CHECK-T2-NEXT:    it lo
+; CHECK-T2-NEXT:    movlo.w r1, #-1
+; CHECK-T2-NEXT:    lsrs r0, r1, #16
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mul r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r2, r0, #16
+; CHECK-ARM-NEXT:    add r1, r2, r1, lsl #16
+; CHECK-ARM-NEXT:    cmp r1, r0, lsl #16
+; CHECK-ARM-NEXT:    mvnlo r1, #0
+; CHECK-ARM-NEXT:    lsr r0, r1, #16
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i16 %y, %z
+  %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)
+  ret i16 %tmp
+}
+
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #24
+; CHECK-T1-NEXT:    lsls r0, r0, #24
+; CHECK-T1-NEXT:    adds r0, r0, r1
+; CHECK-T1-NEXT:    blo .LBB3_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:    mvns r0, r0
+; CHECK-T1-NEXT:  .LBB3_2:
+; CHECK-T1-NEXT:    lsrs r0, r0, #24
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r2, r0, #24
+; CHECK-T2-NEXT:    add.w r1, r2, r1, lsl #24
+; CHECK-T2-NEXT:    cmp.w r1, r0, lsl #24
+; CHECK-T2-NEXT:    it lo
+; CHECK-T2-NEXT:    movlo.w r1, #-1
+; CHECK-T2-NEXT:    lsrs r0, r1, #24
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r2, r0, #24
+; CHECK-ARM-NEXT:    add r1, r2, r1, lsl #24
+; CHECK-ARM-NEXT:    cmp r1, r0, lsl #24
+; CHECK-ARM-NEXT:    mvnlo r1, #0
+; CHECK-ARM-NEXT:    lsr r0, r1, #24
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i8 %y, %z
+  %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)
+  ret i8 %tmp
+}
+
+define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #28
+; CHECK-T1-NEXT:    lsls r0, r0, #28
+; CHECK-T1-NEXT:    adds r0, r0, r1
+; CHECK-T1-NEXT:    blo .LBB4_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:    mvns r0, r0
+; CHECK-T1-NEXT:  .LBB4_2:
+; CHECK-T1-NEXT:    lsrs r0, r0, #28
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r2, r0, #28
+; CHECK-T2-NEXT:    add.w r1, r2, r1, lsl #28
+; CHECK-T2-NEXT:    cmp.w r1, r0, lsl #28
+; CHECK-T2-NEXT:    it lo
+; CHECK-T2-NEXT:    movlo.w r1, #-1
+; CHECK-T2-NEXT:    lsrs r0, r1, #28
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r2, r0, #28
+; CHECK-ARM-NEXT:    add r1, r2, r1, lsl #28
+; CHECK-ARM-NEXT:    cmp r1, r0, lsl #28
+; CHECK-ARM-NEXT:    mvnlo r1, #0
+; CHECK-ARM-NEXT:    lsr r0, r1, #28
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i4 %y, %z
+  %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)
+  ret i4 %tmp
+}
diff --git a/llvm/test/CodeGen/ARM/usub_sat.ll b/llvm/test/CodeGen/ARM/usub_sat.ll
index 5587cef25c3..c080b0286e1 100644
--- a/llvm/test/CodeGen/ARM/usub_sat.ll
+++ b/llvm/test/CodeGen/ARM/usub_sat.ll
@@ -90,7 +90,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
   ret i64 %tmp
 }
 
-define i16 @func16(i16 %x, i16 %y) nounwind {
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
 ; CHECK-T1-LABEL: func16:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r1, r1, #16
@@ -125,7 +125,7 @@ define i16 @func16(i16 %x, i16 %y) nounwind {
   ret i16 %tmp
 }
 
-define i8 @func8(i8 %x, i8 %y) nounwind {
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
 ; CHECK-T1-LABEL: func8:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r1, r1, #24
@@ -160,7 +160,7 @@ define i8 @func8(i8 %x, i8 %y) nounwind {
   ret i8 %tmp
 }
 
-define i4 @func3(i4 %x, i4 %y) nounwind {
+define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
 ; CHECK-T1-LABEL: func3:
 ; CHECK-T1:       @ %bb.0:
 ; CHECK-T1-NEXT:    lsls r1, r1, #28
diff --git a/llvm/test/CodeGen/ARM/usub_sat_plus.ll b/llvm/test/CodeGen/ARM/usub_sat_plus.ll
new file mode 100644
index 00000000000..dc1e6e578de
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/usub_sat_plus.ll
@@ -0,0 +1,218 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
+; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
+; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
+
+declare i4 @llvm.usub.sat.i4(i4, i4)
+declare i8 @llvm.usub.sat.i8(i8, i8)
+declare i16 @llvm.usub.sat.i16(i16, i16)
+declare i32 @llvm.usub.sat.i32(i32, i32)
+declare i64 @llvm.usub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; CHECK-T1-LABEL: func32:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    subs r0, r0, r1
+; CHECK-T1-NEXT:    bhs .LBB0_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:  .LBB0_2:
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func32:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    subs r0, r0, r1
+; CHECK-T2-NEXT:    it lo
+; CHECK-T2-NEXT:    movlo r0, #0
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func32:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mul r1, r1, r2
+; CHECK-ARM-NEXT:    subs r0, r0, r1
+; CHECK-ARM-NEXT:    movlo r0, #0
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i32 %y, %z
+  %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)
+  ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; CHECK-T1-LABEL: func64:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    .save {r4, lr}
+; CHECK-T1-NEXT:    push {r4, lr}
+; CHECK-T1-NEXT:    mov r2, r1
+; CHECK-T1-NEXT:    movs r1, #0
+; CHECK-T1-NEXT:    ldr r4, [sp, #12]
+; CHECK-T1-NEXT:    ldr r3, [sp, #8]
+; CHECK-T1-NEXT:    subs r3, r0, r3
+; CHECK-T1-NEXT:    sbcs r2, r4
+; CHECK-T1-NEXT:    mov r0, r1
+; CHECK-T1-NEXT:    adcs r0, r1
+; CHECK-T1-NEXT:    movs r4, #1
+; CHECK-T1-NEXT:    subs r4, r4, r0
+; CHECK-T1-NEXT:    mov r0, r1
+; CHECK-T1-NEXT:    beq .LBB1_3
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    beq .LBB1_4
+; CHECK-T1-NEXT:  .LBB1_2:
+; CHECK-T1-NEXT:    pop {r4, pc}
+; CHECK-T1-NEXT:  .LBB1_3:
+; CHECK-T1-NEXT:    mov r0, r3
+; CHECK-T1-NEXT:    cmp r4, #0
+; CHECK-T1-NEXT:    bne .LBB1_2
+; CHECK-T1-NEXT:  .LBB1_4:
+; CHECK-T1-NEXT:    mov r1, r2
+; CHECK-T1-NEXT:    pop {r4, pc}
+;
+; CHECK-T2-LABEL: func64:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    ldrd r2, r3, [sp]
+; CHECK-T2-NEXT:    mov.w r12, #0
+; CHECK-T2-NEXT:    subs r0, r0, r2
+; CHECK-T2-NEXT:    sbcs r1, r3
+; CHECK-T2-NEXT:    adc r2, r12, #0
+; CHECK-T2-NEXT:    rsbs.w r2, r2, #1
+; CHECK-T2-NEXT:    itt ne
+; CHECK-T2-NEXT:    movne r0, #0
+; CHECK-T2-NEXT:    movne r1, #0
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func64:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    ldr r2, [sp]
+; CHECK-ARM-NEXT:    mov r12, #0
+; CHECK-ARM-NEXT:    ldr r3, [sp, #4]
+; CHECK-ARM-NEXT:    subs r0, r0, r2
+; CHECK-ARM-NEXT:    sbcs r1, r1, r3
+; CHECK-ARM-NEXT:    adc r2, r12, #0
+; CHECK-ARM-NEXT:    rsbs r2, r2, #1
+; CHECK-ARM-NEXT:    movwne r0, #0
+; CHECK-ARM-NEXT:    movwne r1, #0
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i64 %y, %z
+  %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)
+  ret i64 %tmp
+}
+
+define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func16:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #16
+; CHECK-T1-NEXT:    lsls r0, r0, #16
+; CHECK-T1-NEXT:    subs r0, r0, r1
+; CHECK-T1-NEXT:    bhs .LBB2_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:  .LBB2_2:
+; CHECK-T1-NEXT:    lsrs r0, r0, #16
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func16:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r0, r0, #16
+; CHECK-T2-NEXT:    sub.w r2, r0, r1, lsl #16
+; CHECK-T2-NEXT:    cmp.w r0, r1, lsl #16
+; CHECK-T2-NEXT:    it lo
+; CHECK-T2-NEXT:    movlo r2, #0
+; CHECK-T2-NEXT:    lsrs r0, r2, #16
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func16:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    mul r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r0, r0, #16
+; CHECK-ARM-NEXT:    sub r2, r0, r1, lsl #16
+; CHECK-ARM-NEXT:    cmp r0, r1, lsl #16
+; CHECK-ARM-NEXT:    movlo r2, #0
+; CHECK-ARM-NEXT:    lsr r0, r2, #16
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i16 %y, %z
+  %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
+  ret i16 %tmp
+}
+
+define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func8:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #24
+; CHECK-T1-NEXT:    lsls r0, r0, #24
+; CHECK-T1-NEXT:    subs r0, r0, r1
+; CHECK-T1-NEXT:    bhs .LBB3_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:  .LBB3_2:
+; CHECK-T1-NEXT:    lsrs r0, r0, #24
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func8:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r0, r0, #24
+; CHECK-T2-NEXT:    sub.w r2, r0, r1, lsl #24
+; CHECK-T2-NEXT:    cmp.w r0, r1, lsl #24
+; CHECK-T2-NEXT:    it lo
+; CHECK-T2-NEXT:    movlo r2, #0
+; CHECK-T2-NEXT:    lsrs r0, r2, #24
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func8:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r0, r0, #24
+; CHECK-ARM-NEXT:    sub r2, r0, r1, lsl #24
+; CHECK-ARM-NEXT:    cmp r0, r1, lsl #24
+; CHECK-ARM-NEXT:    movlo r2, #0
+; CHECK-ARM-NEXT:    lsr r0, r2, #24
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i8 %y, %z
+  %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
+  ret i8 %tmp
+}
+
+define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
+; CHECK-T1-LABEL: func4:
+; CHECK-T1:       @ %bb.0:
+; CHECK-T1-NEXT:    muls r1, r2, r1
+; CHECK-T1-NEXT:    lsls r1, r1, #28
+; CHECK-T1-NEXT:    lsls r0, r0, #28
+; CHECK-T1-NEXT:    subs r0, r0, r1
+; CHECK-T1-NEXT:    bhs .LBB4_2
+; CHECK-T1-NEXT:  @ %bb.1:
+; CHECK-T1-NEXT:    movs r0, #0
+; CHECK-T1-NEXT:  .LBB4_2:
+; CHECK-T1-NEXT:    lsrs r0, r0, #28
+; CHECK-T1-NEXT:    bx lr
+;
+; CHECK-T2-LABEL: func4:
+; CHECK-T2:       @ %bb.0:
+; CHECK-T2-NEXT:    muls r1, r2, r1
+; CHECK-T2-NEXT:    lsls r0, r0, #28
+; CHECK-T2-NEXT:    sub.w r2, r0, r1, lsl #28
+; CHECK-T2-NEXT:    cmp.w r0, r1, lsl #28
+; CHECK-T2-NEXT:    it lo
+; CHECK-T2-NEXT:    movlo r2, #0
+; CHECK-T2-NEXT:    lsrs r0, r2, #28
+; CHECK-T2-NEXT:    bx lr
+;
+; CHECK-ARM-LABEL: func4:
+; CHECK-ARM:       @ %bb.0:
+; CHECK-ARM-NEXT:    smulbb r1, r1, r2
+; CHECK-ARM-NEXT:    lsl r0, r0, #28
+; CHECK-ARM-NEXT:    sub r2, r0, r1, lsl #28
+; CHECK-ARM-NEXT:    cmp r0, r1, lsl #28
+; CHECK-ARM-NEXT:    movlo r2, #0
+; CHECK-ARM-NEXT:    lsr r0, r2, #28
+; CHECK-ARM-NEXT:    bx lr
+  %a = mul i4 %y, %z
+  %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
+  ret i4 %tmp
+}