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| author | Sanjay Patel <spatel@rotateright.com> | 2018-12-16 14:57:04 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-12-16 14:57:04 +0000 |
| commit | f24900b9348343f6c415bc164b0745e912e671a5 (patch) | |
| tree | 549f13963b29271a2a4a6a2046acb647e9a6429a /llvm/test/CodeGen/ARM | |
| parent | aad3645fe1b22213d606c54f2342bbcf2871bf15 (diff) | |
| download | bcm5719-llvm-f24900b9348343f6c415bc164b0745e912e671a5.tar.gz bcm5719-llvm-f24900b9348343f6c415bc164b0745e912e671a5.zip | |
[DAGCombiner] allow hoisting vector bitwise logic ahead of truncates
The transform performs a bitwise logic op in a wider type followed by
truncate when both inputs are truncated from the same source type:
logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
There are a bunch of other checks that should prevent doing this when
it might be harmful.
We already do this transform for scalars in this spot. The vector
limitation was shared with a check for the case when the operands are
extended. I'm not sure if that limit is needed either, but that would
be a separate patch.
Differential Revision: https://reviews.llvm.org/D55448
llvm-svn: 349303
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/setcc-logic.ll | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/ARM/setcc-logic.ll b/llvm/test/CodeGen/ARM/setcc-logic.ll index 2c2792ed986..cf482f39f2b 100644 --- a/llvm/test/CodeGen/ARM/setcc-logic.ll +++ b/llvm/test/CodeGen/ARM/setcc-logic.ll @@ -61,9 +61,8 @@ define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> ; CHECK-NEXT: vceq.i32 q8, q9, q8 ; CHECK-NEXT: vld1.64 {d22, d23}, [r0] ; CHECK-NEXT: vceq.i32 q9, q11, q10 +; CHECK-NEXT: vand q8, q8, q9 ; CHECK-NEXT: vmovn.i32 d16, q8 -; CHECK-NEXT: vmovn.i32 d17, q9 -; CHECK-NEXT: vand d16, d16, d17 ; CHECK-NEXT: vmov r0, r1, d16 ; CHECK-NEXT: pop {r11, pc} %cmp1 = icmp eq <4 x i32> %a, %b |
