[ARM] Add cdp intrinsic tests.

- Renamed intrinsics.ll to intrinsics-coprocessor.ll
  as all the tests were testing coprocessor instructions,
  also made the test checks match the full instruction.

Differential Revision: http://reviews.llvm.org/D20393

llvm-svn: 270057

3 files changed, 34 insertions, 8 deletions

diff --git a/llvm/test/CodeGen/ARM/cdp.ll b/llvm/test/CodeGen/ARM/cdp.ll
new file mode 100644
index 00000000000..99ec3b28446
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cdp.ll
@@ -0,0 +1,13 @@
+; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp
+define void @cdp(i32 %a) #0 {
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %1 = load i32, i32* %a.addr, align 4
+  call void @llvm.arm.cdp(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
+  ret void
+}
+
+declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/cdp2.ll b/llvm/test/CodeGen/ARM/cdp2.ll
new file mode 100644
index 00000000000..c2a00d0fdd7
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cdp2.ll
@@ -0,0 +1,13 @@
+; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp2
+define void @cdp2(i32 %a) #0 {
+  %a.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  %1 = load i32, i32* %a.addr, align 4
+  call void @llvm.arm.cdp2(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
+  ret void
+}
+
+declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/intrinsics.ll b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
index 54cc3e0a027..35f916c4a26 100644
--- a/llvm/test/CodeGen/ARM/intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
@@ -3,21 +3,21 @@
 
 define void @coproc() nounwind {
 entry:
-  ; CHECK: mrc
+  ; CHECK: mrc p7, #1, r0, c1, c1, #4
   %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcr
+  ; CHECK: mcr p7, #1, r0, c1, c1, #4
   tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mrc2
+  ; CHECK: mrc2 p7, #1, r1, c1, c1, #4
   %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcr2
+  ; CHECK: mcr2 p7, #1, r1, c1, c1, #4
   tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcrr
+  ; CHECK: mcrr p7, #1, r0, r1, c1
   tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
-  ; CHECK: mcrr2
+  ; CHECK: mcrr2 p7, #1, r0, r1, c1
   tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
-  ; CHECK: cdp
+  ; CHECK: cdp p7, #3, c1, c1, c1, #5
   tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
-  ; CHECK: cdp2
+  ; CHECK: cdp2 p7, #3, c1, c1, c1, #5
   tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
   ret void
 }