[ARM] auto-generate complete checks; NFC

The affected test may change with a patch I'm looking at for DAGCombiner,
so I want to make sure it's not a regression.

llvm-svn: 296175

1 files changed, 34 insertions, 8 deletions

diff --git a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
index 2fb0d231825..76dfb11d44d 100644
--- a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
+++ b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
@@ -1,7 +1,6 @@
 ; RUN: llc -mtriple=arm-eabi -arm-atomic-cfg-tidy=0 %s -o - | FileCheck -check-prefix=ARM %s
 ; RUN: llc -mtriple=thumb-eabi -arm-atomic-cfg-tidy=0 %s -o - | FileCheck -check-prefix=THUMB %s
-; RUN: llc -mtriple=thumb-eabi -arm-atomic-cfg-tidy=0 -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
-; RUN:   | FileCheck -check-prefix=T2 %s
+; RUN: llc -mtriple=thumb-eabi -arm-atomic-cfg-tidy=0 -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck -check-prefix=T2 %s
 ; RUN: llc -mtriple=thumbv8-eabi -arm-atomic-cfg-tidy=0 %s -o - | FileCheck -check-prefix=V8 %s
 
 ; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified.
@@ -93,7 +92,7 @@ entry:
   %1 = load i8, i8* %0, align 1
   %2 = zext i8 %1 to i32
 ; ARM: ands
-; THUMB: ands 
+; THUMB: ands
 ; T2: ands
 ; V8: ands
 ; V8-NEXT: beq
@@ -141,18 +140,45 @@ return:                                           ; preds = %bb2, %bb, %entry
 ; folding of unrelated tests (in this case, a TST against r1 was eliminated in
 ; favour of an AND of r0).
 
+define i32 @test_tst_assessment(i1 %lhs, i1 %rhs) {
 ; ARM-LABEL: test_tst_assessment:
+; ARM:       @ BB#0:
+; ARM-NEXT:    and r0, r0, #1
+; ARM-NEXT:    tst r1, #1
+; ARM-NEXT:    subne r0, r0, #1
+; ARM-NEXT:    mov pc, lr
+;
 ; THUMB-LABEL: test_tst_assessment:
+; THUMB:       @ BB#0:
+; THUMB-NEXT:    movs r2, #1
+; THUMB-NEXT:    ands r2, r0
+; THUMB-NEXT:    subs r0, r2, #1
+; THUMB-NEXT:    lsls r1, r1, #31
+; THUMB-NEXT:    bne .LBB2_2
+; THUMB-NEXT:  @ BB#1:
+; THUMB-NEXT:    push {r2}
+; THUMB-NEXT:    pop {r0}
+; THUMB-NEXT:  .LBB2_2:
+; THUMB-NEXT:    bx lr
+;
 ; T2-LABEL: test_tst_assessment:
+; T2:       @ BB#0:
+; T2-NEXT:    lsls r1, r1, #31
+; T2-NEXT:    and r0, r0, #1
+; T2-NEXT:    it ne
+; T2-NEXT:    subne r0, #1
+; T2-NEXT:    bx lr
+;
 ; V8-LABEL: test_tst_assessment:
-define i32 @test_tst_assessment(i1 %lhs, i1 %rhs) {
+; V8:       @ BB#0:
+; V8-NEXT:    lsls r1, r1, #31
+; V8-NEXT:    and r0, r0, #1
+; V8-NEXT:    it ne
+; V8-NEXT:    subne r0, #1
+; V8-NEXT:    bx lr
   %lhs32 = zext i1 %lhs to i32
   %rhs32 = zext i1 %rhs to i32
   %diff = sub nsw i32 %lhs32, %rhs32
-; ARM: tst r1, #1
-; THUMB: lsls r1, r1, #31
-; T2: lsls r1, r1, #31
-; V8: lsls r1, r1, #31
   ret i32 %diff
 }