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authorMatthias Braun <matze@braunis.de>2015-06-24 20:03:27 +0000
committerMatthias Braun <matze@braunis.de>2015-06-24 20:03:27 +0000
commitba3ecc3c804b05e725f46018690b58acb697f3b7 (patch)
tree518dcf2413ca74a71366161c75842bc45e6b4e9b /llvm/test/CodeGen/ARM
parenta681ea25ede8ce8b65cb6dbc1742406bbaf88afb (diff)
downloadbcm5719-llvm-ba3ecc3c804b05e725f46018690b58acb697f3b7.tar.gz
bcm5719-llvm-ba3ecc3c804b05e725f46018690b58acb697f3b7.zip
ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually test for it
This fixes PR23912 Differential Revision: http://reviews.llvm.org/D10620 llvm-svn: 240582
Diffstat (limited to 'llvm/test/CodeGen/ARM')
-rw-r--r--llvm/test/CodeGen/ARM/ldrd.ll29
1 files changed, 15 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/ARM/ldrd.ll b/llvm/test/CodeGen/ARM/ldrd.ll
index a8070ea68aa..f3e13671ac3 100644
--- a/llvm/test/CodeGen/ARM/ldrd.ll
+++ b/llvm/test/CodeGen/ARM/ldrd.ll
@@ -6,23 +6,24 @@
; Magic ARM pair hints works best with linearscan / fast.
-; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base
-; register when interrupted or faulted.
-
@b = external global i64*
-define i64 @t(i64 %a) nounwind readonly {
-entry:
-; A8-LABEL: t:
-; A8: ldrd r2, r3, [r2]
-
-; M3-LABEL: t:
-; M3-NOT: ldrd
+; We use the following two to force values into specific registers.
+declare i64* @get_ptr()
+declare void @use_i64(i64 %v)
- %0 = load i64*, i64** @b, align 4
- %1 = load i64, i64* %0, align 4
- %2 = mul i64 %1, %a
- ret i64 %2
+define void @test_ldrd(i64 %a) nounwind readonly {
+; CHECK-LABEL: test_ldrd:
+; CHECK: bl{{x?}} _get_ptr
+; A8: ldrd r0, r1, [r0]
+; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base
+; register when interrupted or faulted.
+; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]]
+; CHECK: bl{{x?}} _use_i64
+ %ptr = call i64* @get_ptr()
+ %v = load i64, i64* %ptr, align 8
+ call void @use_i64(i64 %v)
+ ret void
}
; rdar://10435045 mixed LDRi8/LDRi12
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