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| author | Sam Parker <sam.parker@arm.com> | 2017-01-31 14:35:01 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2017-01-31 14:35:01 +0000 |
| commit | 9bf658d5fe3813ebea4f798711ac257c72b1d6b2 (patch) | |
| tree | fd020debbfd2ee840b7f4fe78771396ac792a981 /llvm/test/CodeGen/ARM | |
| parent | af1b9622d4208aa1c60cf8ea49bdc567b189dbb3 (diff) | |
| download | bcm5719-llvm-9bf658d5fe3813ebea4f798711ac257c72b1d6b2.tar.gz bcm5719-llvm-9bf658d5fe3813ebea4f798711ac257c72b1d6b2.zip | |
[ARM] Avoid using ARM instructions in Thumb mode
The Requires class overrides the target requirements of an instruction,
rather than adding to them, so all ARM instructions need to include the
IsARM predicate when they have overwitten requirements.
This caused the swp and swpb instructions to be allowed in thumb mode
assembly, and the ARM encoding of CDP to be selected in codegen (which
is different for conditional instructions).
Differential Revision: https://reviews.llvm.org/D29283
llvm-svn: 293634
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll index 5d59fc64d92..e5c2fb4d67a 100644 --- a/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll +++ b/llvm/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll @@ -1,5 +1,4 @@ ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s ; PR4091 define void @foo(i32 %i, i32* %p) nounwind { diff --git a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll index 8fea49b39fb..5352471238f 100644 --- a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll +++ b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s define void @coproc(i8* %i) nounwind { entry: |
