[SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value.

This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits.

Differential Revision: https://reviews.llvm.org/D72573

2 files changed, 16 insertions, 75 deletions

diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index cc97f2f0155..bf029ee862a 100644
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -967,52 +967,25 @@ define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
   ret i1 %res
 }
 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
-; ARM6-LABEL: scalar_i32_x_is_const2_eq:
-; ARM6:       @ %bb.0:
-; ARM6-NEXT:    ldr r2, .LCPI19_0
-; ARM6-NEXT:    mov r1, #1
-; ARM6-NEXT:    and r0, r2, r1, lsr r0
-; ARM6-NEXT:    clz r0, r0
-; ARM6-NEXT:    lsr r0, r0, #5
-; ARM6-NEXT:    bx lr
-; ARM6-NEXT:    .p2align 2
-; ARM6-NEXT:  @ %bb.1:
-; ARM6-NEXT:  .LCPI19_0:
-; ARM6-NEXT:    .long 2857740885 @ 0xaa55aa55
-;
-; ARM78-LABEL: scalar_i32_x_is_const2_eq:
-; ARM78:       @ %bb.0:
-; ARM78-NEXT:    movw r1, #43605
-; ARM78-NEXT:    mov r2, #1
-; ARM78-NEXT:    movt r1, #43605
-; ARM78-NEXT:    and r0, r1, r2, lsr r0
-; ARM78-NEXT:    clz r0, r0
-; ARM78-NEXT:    lsr r0, r0, #5
-; ARM78-NEXT:    bx lr
+; ARM-LABEL: scalar_i32_x_is_const2_eq:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    mov r1, #1
+; ARM-NEXT:    eor r0, r1, r1, lsr r0
+; ARM-NEXT:    bx lr
 ;
 ; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
 ; THUMB6:       @ %bb.0:
 ; THUMB6-NEXT:    movs r1, #1
 ; THUMB6-NEXT:    lsrs r1, r0
-; THUMB6-NEXT:    ldr r2, .LCPI19_0
-; THUMB6-NEXT:    ands r2, r1
-; THUMB6-NEXT:    rsbs r0, r2, #0
-; THUMB6-NEXT:    adcs r0, r2
+; THUMB6-NEXT:    rsbs r0, r1, #0
+; THUMB6-NEXT:    adcs r0, r1
 ; THUMB6-NEXT:    bx lr
-; THUMB6-NEXT:    .p2align 2
-; THUMB6-NEXT:  @ %bb.1:
-; THUMB6-NEXT:  .LCPI19_0:
-; THUMB6-NEXT:    .long 2857740885 @ 0xaa55aa55
 ;
 ; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
 ; THUMB78:       @ %bb.0:
 ; THUMB78-NEXT:    movs r1, #1
 ; THUMB78-NEXT:    lsr.w r0, r1, r0
-; THUMB78-NEXT:    movw r1, #43605
-; THUMB78-NEXT:    movt r1, #43605
-; THUMB78-NEXT:    ands r0, r1
-; THUMB78-NEXT:    clz r0, r0
-; THUMB78-NEXT:    lsrs r0, r0, #5
+; THUMB78-NEXT:    eor r0, r0, #1
 ; THUMB78-NEXT:    bx lr
   %t0 = lshr i32 1, %y
   %t1 = and i32 %t0, 2857740885
@@ -1029,8 +1002,7 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    uxtb r1, r1
 ; ARM6-NEXT:    mov r2, #24
-; ARM6-NEXT:    and r0, r0, r2, lsr r1
-; ARM6-NEXT:    sxtb r1, r0
+; ARM6-NEXT:    and r1, r0, r2, lsr r1
 ; ARM6-NEXT:    mov r0, #0
 ; ARM6-NEXT:    cmp r1, #0
 ; ARM6-NEXT:    movmi r0, #1
@@ -1040,8 +1012,7 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    uxtb r1, r1
 ; ARM78-NEXT:    mov r2, #24
-; ARM78-NEXT:    and r0, r0, r2, lsr r1
-; ARM78-NEXT:    sxtb r1, r0
+; ARM78-NEXT:    and r1, r0, r2, lsr r1
 ; ARM78-NEXT:    mov r0, #0
 ; ARM78-NEXT:    cmp r1, #0
 ; ARM78-NEXT:    movwmi r0, #1
@@ -1053,8 +1024,6 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; THUMB6-NEXT:    movs r2, #24
 ; THUMB6-NEXT:    lsrs r2, r1
 ; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    sxtb r0, r2
-; THUMB6-NEXT:    cmp r0, #0
 ; THUMB6-NEXT:    bmi .LBB20_2
 ; THUMB6-NEXT:  @ %bb.1:
 ; THUMB6-NEXT:    movs r0, #0
@@ -1069,9 +1038,7 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 ; THUMB78-NEXT:    movs r2, #24
 ; THUMB78-NEXT:    lsr.w r1, r2, r1
 ; THUMB78-NEXT:    ands r0, r1
-; THUMB78-NEXT:    sxtb r1, r0
-; THUMB78-NEXT:    movs r0, #0
-; THUMB78-NEXT:    cmp r1, #0
+; THUMB78-NEXT:    mov.w r0, #0
 ; THUMB78-NEXT:    it mi
 ; THUMB78-NEXT:    movmi r0, #1
 ; THUMB78-NEXT:    bx lr
@@ -1087,8 +1054,7 @@ define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; ARM-NEXT:    uxtb r1, r1
 ; ARM-NEXT:    mov r2, #128
 ; ARM-NEXT:    and r0, r0, r2, lsr r1
-; ARM-NEXT:    mvn r1, #0
-; ARM-NEXT:    uxtab r0, r1, r0
+; ARM-NEXT:    sub r0, r0, #1
 ; ARM-NEXT:    clz r0, r0
 ; ARM-NEXT:    lsr r0, r0, #5
 ; ARM-NEXT:    bx lr
@@ -1099,8 +1065,7 @@ define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; THUMB6-NEXT:    movs r2, #128
 ; THUMB6-NEXT:    lsrs r2, r1
 ; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    uxtb r0, r2
-; THUMB6-NEXT:    subs r1, r0, #1
+; THUMB6-NEXT:    subs r1, r2, #1
 ; THUMB6-NEXT:    rsbs r0, r1, #0
 ; THUMB6-NEXT:    adcs r0, r1
 ; THUMB6-NEXT:    bx lr
@@ -1111,8 +1076,7 @@ define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; THUMB78-NEXT:    movs r2, #128
 ; THUMB78-NEXT:    lsr.w r1, r2, r1
 ; THUMB78-NEXT:    ands r0, r1
-; THUMB78-NEXT:    mov.w r1, #-1
-; THUMB78-NEXT:    uxtab r0, r1, r0
+; THUMB78-NEXT:    subs r0, #1
 ; THUMB78-NEXT:    clz r0, r0
 ; THUMB78-NEXT:    lsrs r0, r0, #5
 ; THUMB78-NEXT:    bx lr
diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index b59c8a1d955..0de18e55722 100644
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -24,7 +24,6 @@ define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
 ; ARM-NEXT:    uxtb r0, r0
 ; ARM-NEXT:    lsr r0, r0, r1
 ; ARM-NEXT:    mov r1, #1
-; ARM-NEXT:    uxtb r0, r0
 ; ARM-NEXT:    eor r0, r1, r0, lsr #7
 ; ARM-NEXT:    bx lr
 ;
@@ -45,7 +44,6 @@ define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
 ; THUMB7-NEXT:    uxtb r0, r0
 ; THUMB7-NEXT:    lsrs r0, r1
 ; THUMB7-NEXT:    movs r1, #1
-; THUMB7-NEXT:    uxtb r0, r0
 ; THUMB7-NEXT:    eor.w r0, r1, r0, lsr #7
 ; THUMB7-NEXT:    bx lr
 ;
@@ -55,7 +53,6 @@ define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
 ; THUMB8-NEXT:    uxtb r1, r1
 ; THUMB8-NEXT:    lsrs r0, r1
 ; THUMB8-NEXT:    movs r1, #1
-; THUMB8-NEXT:    uxtb r0, r0
 ; THUMB8-NEXT:    eor.w r0, r1, r0, lsr #7
 ; THUMB8-NEXT:    bx lr
   %t0 = shl i8 128, %y
@@ -163,7 +160,6 @@ define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
 ; ARM-NEXT:    uxth r0, r0
 ; ARM-NEXT:    lsr r0, r0, r1
 ; ARM-NEXT:    mov r1, #1
-; ARM-NEXT:    uxth r0, r0
 ; ARM-NEXT:    eor r0, r1, r0, lsr #15
 ; ARM-NEXT:    bx lr
 ;
@@ -185,7 +181,6 @@ define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
 ; THUMB7-NEXT:    uxth r0, r0
 ; THUMB7-NEXT:    lsrs r0, r1
 ; THUMB7-NEXT:    movs r1, #1
-; THUMB7-NEXT:    uxth r0, r0
 ; THUMB7-NEXT:    eor.w r0, r1, r0, lsr #15
 ; THUMB7-NEXT:    bx lr
 ;
@@ -195,7 +190,6 @@ define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
 ; THUMB8-NEXT:    uxth r1, r1
 ; THUMB8-NEXT:    lsrs r0, r1
 ; THUMB8-NEXT:    movs r1, #1
-; THUMB8-NEXT:    uxth r0, r0
 ; THUMB8-NEXT:    eor.w r0, r1, r0, lsr #15
 ; THUMB8-NEXT:    bx lr
   %t0 = shl i16 32768, %y
@@ -973,7 +967,6 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
 ; ARM-NEXT:    uxtb r1, r1
 ; ARM-NEXT:    uxtb r0, r0
 ; ARM-NEXT:    lsr r0, r0, r1
-; ARM-NEXT:    uxtb r0, r0
 ; ARM-NEXT:    lsr r0, r0, #7
 ; ARM-NEXT:    bx lr
 ;
@@ -982,7 +975,6 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
 ; THUMB6-NEXT:    uxtb r1, r1
 ; THUMB6-NEXT:    uxtb r0, r0
 ; THUMB6-NEXT:    lsrs r0, r1
-; THUMB6-NEXT:    uxtb r0, r0
 ; THUMB6-NEXT:    lsrs r0, r0, #7
 ; THUMB6-NEXT:    bx lr
 ;
@@ -991,7 +983,6 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
 ; THUMB7-NEXT:    uxtb r1, r1
 ; THUMB7-NEXT:    uxtb r0, r0
 ; THUMB7-NEXT:    lsrs r0, r1
-; THUMB7-NEXT:    uxtb r0, r0
 ; THUMB7-NEXT:    lsrs r0, r0, #7
 ; THUMB7-NEXT:    bx lr
 ;
@@ -1000,7 +991,6 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
 ; THUMB8-NEXT:    uxtb r0, r0
 ; THUMB8-NEXT:    uxtb r1, r1
 ; THUMB8-NEXT:    lsrs r0, r1
-; THUMB8-NEXT:    uxtb r0, r0
 ; THUMB8-NEXT:    lsrs r0, r0, #7
 ; THUMB8-NEXT:    bx lr
   %t0 = shl i8 128, %y
@@ -1178,13 +1168,7 @@ define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; ARM:       @ %bb.0:
-; ARM-NEXT:    uxtb r1, r1
-; ARM-NEXT:    mvn r2, #127
-; ARM-NEXT:    and r0, r0, r2, lsl r1
-; ARM-NEXT:    mvn r1, #0
-; ARM-NEXT:    uxtab r0, r1, r0
-; ARM-NEXT:    clz r0, r0
-; ARM-NEXT:    lsr r0, r0, #5
+; ARM-NEXT:    mov r0, #0
 ; ARM-NEXT:    bx lr
 ;
 ; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
@@ -1202,14 +1186,7 @@ define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ;
 ; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; THUMB78:       @ %bb.0:
-; THUMB78-NEXT:    uxtb r1, r1
-; THUMB78-NEXT:    mvn r2, #127
-; THUMB78-NEXT:    lsl.w r1, r2, r1
-; THUMB78-NEXT:    ands r0, r1
-; THUMB78-NEXT:    mov.w r1, #-1
-; THUMB78-NEXT:    uxtab r0, r1, r0
-; THUMB78-NEXT:    clz r0, r0
-; THUMB78-NEXT:    lsrs r0, r0, #5
+; THUMB78-NEXT:    movs r0, #0
 ; THUMB78-NEXT:    bx lr
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x