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| author | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2019-12-03 10:40:03 -0800 |
|---|---|---|
| committer | Aditya Nandakumar <aditya_nandakumar@apple.com> | 2019-12-03 10:41:10 -0800 |
| commit | 6da7dbb806dce9fbc05416482a5b895efdea96b0 (patch) | |
| tree | fb4c8d1f35cd60b7424e6eab9643aab2e4c65bc7 /llvm/test/CodeGen/ARM | |
| parent | 444ac34182d562db2cb3b7d93d0d63acca1a6c9a (diff) | |
| download | bcm5719-llvm-6da7dbb806dce9fbc05416482a5b895efdea96b0.tar.gz bcm5719-llvm-6da7dbb806dce9fbc05416482a5b895efdea96b0.zip | |
[GlobalISel]: Allow targets to override how to widen constants during legalization
https://reviews.llvm.org/D70922
This adds a hook to allow targets to define exactly what extension
operation should be performed for widening constants. This handles cases
like widening i1 true which would end up becoming -1 which affects code
quality during combines.
Additionally, in order to stay consistent with how DAG is promoting
constants, we now signextend for byte sized types and zero extend
otherwise (by default). Targets can of course override this if
necessary.
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir | 8 |
2 files changed, 4 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir index de5545594bf..9d662092110 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir @@ -44,7 +44,7 @@ body: | %3(s1) = G_CONSTANT i1 1 G_STORE %3(s1), %4(p0) :: (store 1) ; CHECK-NOT: G_CONSTANT i1 - ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32) ; CHECK-NOT: G_CONSTANT i1 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir index b413130558e..0cdab2c41f7 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir @@ -1131,10 +1131,9 @@ body: | ; SOFT-NOT: G_FCMP ; For soft float we just need to return a '-1' constant, but the truncation ; to 1 bit is converted by the combiner to the following masking sequence. - ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32) - ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] + ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[R]] ; SOFT-NOT: G_FCMP ; CHECK: $r0 = COPY [[REXT]] ... @@ -1853,11 +1852,10 @@ body: | ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]] ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-NOT: G_FCMP - ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 ; The result needs to be truncated, and the combiner turns the truncation ; into the following masking sequence. ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] + ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-NOT: G_FCMP %7(s32) = G_ZEXT %6(s1) |
