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authorStepan Dyatkovskiy <stpworld@narod.ru>2012-08-20 07:57:06 +0000
committerStepan Dyatkovskiy <stpworld@narod.ru>2012-08-20 07:57:06 +0000
commit6a638ec521e9fad6ff06b098653d7be2b87ad9e3 (patch)
tree1777cdbb4a4ace68970625625bed3ee93851d35c /llvm/test/CodeGen/ARM
parentb58eec4eaf52a918c4f7afac55afaf17c851f82a (diff)
downloadbcm5719-llvm-6a638ec521e9fad6ff06b098653d7be2b87ad9e3.tar.gz
bcm5719-llvm-6a638ec521e9fad6ff06b098653d7be2b87ad9e3.zip
Fixed DAGCombiner bug (found and localized by James Malloy):
The DAGCombiner tries to optimise a BUILD_VECTOR by checking if it consists purely of get_vector_elts from one or two source vectors. If so, it either makes a concat_vectors node or a shufflevector node. However, it doesn't check the element type width of the underlying vector, so if you have this sequence: Node0: v4i16 = ... Node1: i32 = extract_vector_elt Node0 Node2: i32 = extract_vector_elt Node0 Node3: v16i8 = BUILD_VECTOR Node1, Node2, ... It will attempt to: Node0: v4i16 = ... NewNode1: v16i8 = concat_vectors Node0, ... Where this is actually invalid because the element width is completely different. This causes an assertion failure on DAG legalization stage. Fix: If output item type of BUILD_VECTOR differs from input item type. Make concat_vectors based on input element type and then bitcast it to the output vector type. So the case described above will transformed to: Node0: v4i16 = ... NewNode1: v8i16 = concat_vectors Node0, ... NewNode2: v16i8 = bitcast NewNode1 llvm-svn: 162195
Diffstat (limited to 'llvm/test/CodeGen/ARM')
0 files changed, 0 insertions, 0 deletions
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