Fix ARM paired GPR COPY lowering

ARM paired GPR COPY was being lowered to two MOVr without CC. This
patch puts the CC back.

My test is a reduction of the case where I encountered the issue,
64-bit atomics use paired GPRs.

The issue only occurs with selectionDAG, FastISel doesn't encounter it
so I didn't bother calling it.

llvm-svn: 186226

1 files changed, 17 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/ARM/copy-paired-reg.ll b/llvm/test/CodeGen/ARM/copy-paired-reg.ll
new file mode 100644
index 00000000000..17a4461c682
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/copy-paired-reg.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -verify-machineinstrs
+
+define void @f() {
+  %a = alloca i8, i32 8, align 8
+  %b = alloca i8, i32 8, align 8
+
+  %c = bitcast i8* %a to i64*
+  %d = bitcast i8* %b to i64*
+
+  store atomic i64 0, i64* %c seq_cst, align 8
+  store atomic i64 0, i64* %d seq_cst, align 8
+
+  %e = load atomic i64* %d seq_cst, align 8
+
+  ret void
+}