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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-02-14 15:09:09 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-02-14 15:09:09 +0000 |
| commit | 3b4294edd2c6a2e10b502665b4648968c62ff055 (patch) | |
| tree | 77f382f452973236aba0bf7bc36c85c8ef78154c /llvm/test/CodeGen/ARM | |
| parent | ded6e7a26303af2148be15db663ec887b028e31c (diff) | |
| download | bcm5719-llvm-3b4294edd2c6a2e10b502665b4648968c62ff055.tar.gz bcm5719-llvm-3b4294edd2c6a2e10b502665b4648968c62ff055.zip | |
[ARM] f16 stack spill/reloads
This adds support for handling f16 stack spills/reloads.
Differential Revision: https://reviews.llvm.org/D43280
llvm-svn: 325130
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fp16-instructions.ll | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/fp16-instructions.ll b/llvm/test/CodeGen/ARM/fp16-instructions.ll index b2b31672ce7..e0c6e5c1f90 100644 --- a/llvm/test/CodeGen/ARM/fp16-instructions.ll +++ b/llvm/test/CodeGen/ARM/fp16-instructions.ll @@ -11,6 +11,10 @@ ; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16 ; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16 +; Test fast-isel +; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16 -O0 | FileCheck %s --check-prefixes=CHECK-SPILL-RELOAD +; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+fullfp16 -O0 | FileCheck %s --check-prefixes=CHECK-SPILL-RELOAD + ; HARD: ; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3 | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-VFP3 ; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FP16 @@ -719,3 +723,25 @@ entry: ; CHECK-SOFTFP-FULLFP16: vldr.16 [[S2:s[0-9]]], [sp, #{{.}}] ; CHECK-SOFTFP-FULLFP16: vadd.f16 s{{.}}, [[S2]], [[S0_2]] } + +; Test function calls to check store/load reg to/from stack +define i32 @fn1() { +entry: + %coerce = alloca half, align 2 + %tmp2 = alloca i32, align 4 + store half 0xH7C00, half* %coerce, align 2 + %0 = load i32, i32* %tmp2, align 4 + %call = call i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 %0) + store half 0xH7C00, half* %coerce, align 2 + %1 = load i32, i32* %tmp2, align 4 + %call3 = call i32 bitcast (i32 (...)* @fn3 to i32 (i32)*)(i32 %1) + ret i32 %call3 + +; CHECK-SPILL-RELOAD-LABEL: fn1: +; CHECK-SPILL-RELOAD: vstr.16 s0, [sp, #{{.}}] @ 2-byte Spill +; CHECK-SPILL-RELOAD-NEXT: bl fn2 +; CHECK-SPILL-RELOAD-NEXT: vldr.16 s0, [sp, #{{.}}] @ 2-byte Reload +} + +declare dso_local i32 @fn2(...) +declare dso_local i32 @fn3(...) |
