[ARM] Add backend support for load/store intrinsics.

Added support to map intrinsics
__builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l}
to their ARM instructions.

Differential Revision: http://reviews.llvm.org/D20564

llvm-svn: 271271

3 files changed, 61 insertions, 7 deletions

diff --git a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
index 35f916c4a26..ccaf5c29fad 100644
--- a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
+++ b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
@@ -1,27 +1,59 @@
 ; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
 ; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
 
-define void @coproc() nounwind {
+define void @coproc(i8* %i) nounwind {
 entry:
-  ; CHECK: mrc p7, #1, r0, c1, c1, #4
+  ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
   %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcr p7, #1, r0, c1, c1, #4
+  ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
   tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mrc2 p7, #1, r1, c1, c1, #4
+  ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
   %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcr2 p7, #1, r1, c1, c1, #4
+  ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
   tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
-  ; CHECK: mcrr p7, #1, r0, r1, c1
+  ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
   tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
-  ; CHECK: mcrr2 p7, #1, r0, r1, c1
+  ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
   tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
   ; CHECK: cdp p7, #3, c1, c1, c1, #5
   tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
   ; CHECK: cdp2 p7, #3, c1, c1, c1, #5
   tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
+  ; CHECK: ldc p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
+  ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
+  ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
+  ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
+  ; CHECK: stc p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
+  ; CHECK: stcl p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
+  ; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
+  ; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
+  tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
   ret void
 }
 
+declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
+
+declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
+
+declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
+
+declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
+
+declare void @llvm.arm.stc(i32, i32, i8*) nounwind
+
+declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
+
+declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
+
+declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
+
 declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
 
 declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
diff --git a/llvm/test/CodeGen/ARM/ldc2l.ll b/llvm/test/CodeGen/ARM/ldc2l.ll
new file mode 100644
index 00000000000..58d9509b167
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/ldc2l.ll
@@ -0,0 +1,11 @@
+; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ldc2l
+define void @ldc2l(i8* %i) nounwind {
+entry:
+  call void @llvm.arm.ldc2l(i32 1, i32 2, i8* %i) nounwind
+  ret void
+}
+
+declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
diff --git a/llvm/test/CodeGen/ARM/stc2.ll b/llvm/test/CodeGen/ARM/stc2.ll
new file mode 100644
index 00000000000..1127796387b
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/stc2.ll
@@ -0,0 +1,11 @@
+; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.stc2
+define void @stc2(i8* %i) nounwind {
+entry:
+  call void @llvm.arm.stc2(i32 1, i32 2, i8* %i) nounwind
+  ret void
+}
+
+declare void @llvm.arm.stc2(i32, i32, i8*) nounwind