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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-05-03 17:29:22 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-05-03 17:29:22 +0000 |
| commit | 168c9005b5c71737913554ed512ad5f2c54d9c43 (patch) | |
| tree | e1e036b0cd5f8502ffebfbfdf3298ac2d77cf092 /llvm/test/CodeGen/ARM | |
| parent | 990a969892c93ab070ac495fdcff58acc716bc5c (diff) | |
| download | bcm5719-llvm-168c9005b5c71737913554ed512ad5f2c54d9c43.tar.gz bcm5719-llvm-168c9005b5c71737913554ed512ad5f2c54d9c43.zip | |
Add a few ARM coprocessor intrinsics. Testcases included
llvm-svn: 130763
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/intrinsics.ll | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/intrinsics.ll b/llvm/test/CodeGen/ARM/intrinsics.ll new file mode 100644 index 00000000000..54cc3e0a027 --- /dev/null +++ b/llvm/test/CodeGen/ARM/intrinsics.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s + +define void @coproc() nounwind { +entry: + ; CHECK: mrc + %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcr + tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind + ; CHECK: mrc2 + %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcr2 + tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcrr + tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind + ; CHECK: mcrr2 + tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind + ; CHECK: cdp + tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind + ; CHECK: cdp2 + tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind + ret void +} + +declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind + +declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind + +declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind |
