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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-05-06 00:58:00 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-05-06 00:58:00 +0000 |
| commit | 16547c4e315232b9b8b725652a28ce027777936b (patch) | |
| tree | 9c75dc2e7fa96a6970eab9633d4e038ce89333ad /llvm/test/CodeGen/ARM | |
| parent | 31f9f6100efa23a26f4156eb3bca238e2f96c49f (diff) | |
| download | bcm5719-llvm-16547c4e315232b9b8b725652a28ce027777936b.tar.gz bcm5719-llvm-16547c4e315232b9b8b725652a28ce027777936b.zip | |
[CodeGen] Round [SU]INT_TO_FP result when promoting from f16.
If we don't, values that aren't precisely representable in f16 could
be used as-is in a promoted f32 operation, which would produce
incorrect results.
AArch64 had the correct behavior; add a focused test.
Fixes http://llvm.org/PR26871
llvm-svn: 268700
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fp16-promote.ll | 40 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fp16-v3.ll | 12 |
2 files changed, 47 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/ARM/fp16-promote.ll b/llvm/test/CodeGen/ARM/fp16-promote.ll index 2a2eb8d2b6b..4da56b7ef35 100644 --- a/llvm/test/CodeGen/ARM/fp16-promote.ll +++ b/llvm/test/CodeGen/ARM/fp16-promote.ll @@ -889,4 +889,44 @@ define half @test_struct_arg(%struct.dummy %p) { ret half %a } +; CHECK-LABEL: test_uitofp_i32_fadd: +; CHECK-VFP-DAG: vcvt.f32.u32 +; CHECK-NOVFP-DAG: bl __aeabi_ui2f + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-FP16-DAG: vcvtb.f32.f16 +; CHECK-LIBCALL-DAG: bl __aeabi_h2f +; CHECK-LIBCALL-DAG: bl __aeabi_h2f + +; CHECK-VFP-DAG: vadd.f32 +; CHECK-NOVFP-DAG: bl __aeabi_fadd + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-LIBCALL-DAG: bl __aeabi_f2h +define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 { + %c = uitofp i32 %a to half + %r = fadd half %b, %c + ret half %r +} + +; CHECK-LABEL: test_sitofp_i32_fadd: +; CHECK-VFP-DAG: vcvt.f32.s32 +; CHECK-NOVFP-DAG: bl __aeabi_i2f + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-FP16-DAG: vcvtb.f32.f16 +; CHECK-LIBCALL-DAG: bl __aeabi_h2f +; CHECK-LIBCALL-DAG: bl __aeabi_h2f + +; CHECK-VFP-DAG: vadd.f32 +; CHECK-NOVFP-DAG: bl __aeabi_fadd + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-LIBCALL-DAG: bl __aeabi_f2h +define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 { + %c = sitofp i32 %a to half + %r = fadd half %b, %c + ret half %r +} + attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/ARM/fp16-v3.ll b/llvm/test/CodeGen/ARM/fp16-v3.ll index 4a120723542..e26455e61e7 100644 --- a/llvm/test/CodeGen/ARM/fp16-v3.ll +++ b/llvm/test/CodeGen/ARM/fp16-v3.ll @@ -4,11 +4,13 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv7a--none-eabi" ; CHECK-LABEL: test_vec3: -; CHECK: vcvtb.f32.f16 -; CHECK: vcvt.f32.s32 -; CHECK: vadd.f32 -; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}} -; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]] +; CHECK-DAG: vcvtb.f32.f16 [[SREG1:s[0-9]+]], +; CHECK-DAG: vcvt.f32.s32 [[SREG2:s[0-9]+]], +; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]] +; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]] +; CHECK: vadd.f32 [[SREG5:s[0-9]+]], [[SREG4]], [[SREG1]] +; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]] +; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG6]] ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]] ; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16 ; CHECK-DAG: strh [[RREG1]], [r0, #4] |
