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| author | Momchil Velikov <momchil.velikov@arm.com> | 2019-11-18 18:03:41 +0000 |
|---|---|---|
| committer | Momchil Velikov <momchil.velikov@arm.com> | 2019-11-25 18:26:12 +0000 |
| commit | 09555ce07176d279e8ba8bdb74bb8dbff0a3cb82 (patch) | |
| tree | 9bed2d43eb28a608ea29fd70dda688cf8b4bbbde /llvm/test/CodeGen/ARM | |
| parent | a7d3f6933ddbbd1c0b20529a0734ed66f98d75a0 (diff) | |
| download | bcm5719-llvm-09555ce07176d279e8ba8bdb74bb8dbff0a3cb82.tar.gz bcm5719-llvm-09555ce07176d279e8ba8bdb74bb8dbff0a3cb82.zip | |
[ARM] Generate CMSE instructions from CMSE intrinsics
This patch adds instruction selection patterns for the TT, TTT, TTA, and TTAT
instructions and tests for llvm.arm.cmse.tt, llvm.arm.cmse.ttt,
llvm.arm.cmse.tta, and llvm.arm.cmse.ttat intrinsics (added in a previous
patch).
Patch by Javed Absar.
Differential Revision: https://reviews.llvm.org/D70407
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/intrinsics-cmse.ll | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/intrinsics-cmse.ll b/llvm/test/CodeGen/ARM/intrinsics-cmse.ll new file mode 100644 index 00000000000..be4fed19665 --- /dev/null +++ b/llvm/test/CodeGen/ARM/intrinsics-cmse.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -mtriple=thumbv8m.base | FileCheck %s +; RUN: llc < %s -mtriple=thumbebv8m.base | FileCheck %s + +define i32 @test_tt(i8* readnone %p) #0 { +entry: + %0 = tail call i32 @llvm.arm.cmse.tt(i8* %p) + ret i32 %0 +} +; CHECK-LABEL: test_tt: +; CHECK: tt r{{[0-9]+}}, r{{[0-9]+}} + +declare i32 @llvm.arm.cmse.tt(i8*) #1 + +define i32 @test_ttt(i8* readnone %p) #0 { +entry: + %0 = tail call i32 @llvm.arm.cmse.ttt(i8* %p) + ret i32 %0 +} +; CHECK-LABEL: test_ttt: +; CHECK: ttt r{{[0-9]+}}, r{{[0-9]+}} + +declare i32 @llvm.arm.cmse.ttt(i8*) #1 + +define i32 @test_tta(i8* readnone %p) #0 { +entry: + %0 = tail call i32 @llvm.arm.cmse.tta(i8* %p) + ret i32 %0 +} +; CHECK-LABEL: test_tta: +; CHECK: tta r{{[0-9]+}}, r{{[0-9]+}} + +declare i32 @llvm.arm.cmse.tta(i8*) #1 + +define i32 @test_ttat(i8* readnone %p) #0 { +entry: + %0 = tail call i32 @llvm.arm.cmse.ttat(i8* %p) + ret i32 %0 +} +; CHECK-LABEL: test_ttat: +; CHECK: ttat r{{[0-9]+}}, r{{[0-9]+}} + +declare i32 @llvm.arm.cmse.ttat(i8*) #1 + +attributes #0 = { nounwind readnone "target-features"="+8msecext"} +attributes #1 = { nounwind readnone } |
