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| author | Evan Cheng <evan.cheng@apple.com> | 2011-04-19 00:04:03 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-04-19 00:04:03 +0000 |
| commit | 4079133796951d2978b19947227d62a8bef016e2 (patch) | |
| tree | f33e3eb9b64207d5688535c10b3ca02274aed626 /llvm/test/CodeGen/ARM/vldlane.ll | |
| parent | 939efc5b0d50e8f60c8070020d82b2a87cfc4356 (diff) | |
| download | bcm5719-llvm-4079133796951d2978b19947227d62a8bef016e2.tar.gz bcm5719-llvm-4079133796951d2978b19947227d62a8bef016e2.zip | |
Do not lose mem_operands while lowering VLD / VST intrinsics.
llvm-svn: 129738
Diffstat (limited to 'llvm/test/CodeGen/ARM/vldlane.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/vldlane.ll | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/vldlane.ll b/llvm/test/CodeGen/ARM/vldlane.ll index 68dd503bcc4..805aad51d4f 100644 --- a/llvm/test/CodeGen/ARM/vldlane.ll +++ b/llvm/test/CodeGen/ARM/vldlane.ll @@ -491,7 +491,7 @@ declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x flo ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.) -define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { +define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { ;CHECK: test_qqqq_regsequence_subreg ;CHECK: vld3.16 %tmp63 = extractvalue [6 x i64] %b, 5 @@ -500,8 +500,12 @@ define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { %ins67 = or i128 %tmp65, 0 %tmp78 = bitcast i128 %ins67 to <8 x i16> %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) - call void @llvm.trap() - unreachable + %tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0 + %tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1 + %tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2 + %tmp6 = add <8 x i16> %tmp3, %tmp4 + %tmp7 = add <8 x i16> %tmp5, %tmp6 + ret <8 x i16> %tmp7 } declare void @llvm.trap() nounwind |
