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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 01:49:06 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 01:49:06 +0000 |
| commit | ff1c862f8e8028dccf3cf65a75f2e4e0f198fe12 (patch) | |
| tree | 680d8946b1102f4b24b68792bd0b0788ed6b2b73 /llvm/test/CodeGen/ARM/fadds.ll | |
| parent | 523fa3a2e88c4f7d47e77c86eb54a22e277ed471 (diff) | |
| download | bcm5719-llvm-ff1c862f8e8028dccf3cf65a75f2e4e0f198fe12.tar.gz bcm5719-llvm-ff1c862f8e8028dccf3cf65a75f2e4e0f198fe12.zip | |
- Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
Diffstat (limited to 'llvm/test/CodeGen/ARM/fadds.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fadds.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/ARM/fadds.ll b/llvm/test/CodeGen/ARM/fadds.ll index 113f0e29bd1..749690e98d0 100644 --- a/llvm/test/CodeGen/ARM/fadds.ll +++ b/llvm/test/CodeGen/ARM/fadds.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vadd.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vadd.f32 s0, s0, s1 +; CORTEXA9: vadd.f32 s0, s1, s0 |
