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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 01:49:06 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-28 01:49:06 +0000 |
| commit | ff1c862f8e8028dccf3cf65a75f2e4e0f198fe12 (patch) | |
| tree | 680d8946b1102f4b24b68792bd0b0788ed6b2b73 /llvm/test | |
| parent | 523fa3a2e88c4f7d47e77c86eb54a22e277ed471 (diff) | |
| download | bcm5719-llvm-ff1c862f8e8028dccf3cf65a75f2e4e0f198fe12.tar.gz bcm5719-llvm-ff1c862f8e8028dccf3cf65a75f2e4e0f198fe12.zip | |
- Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/fabss.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fadds.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fdivs.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fmacs.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fmscs.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fmuls.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/shifter_operand.ll | 2 |
7 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/ARM/fabss.ll b/llvm/test/CodeGen/ARM/fabss.ll index dfc1e0a957c..f03282bdab7 100644 --- a/llvm/test/CodeGen/ARM/fabss.ll +++ b/llvm/test/CodeGen/ARM/fabss.ll @@ -24,4 +24,4 @@ declare float @fabsf(float) ; CORTEXA8: test: ; CORTEXA8: vabs.f32 d1, d1 ; CORTEXA9: test: -; CORTEXA9: vabs.f32 s0, s0 +; CORTEXA9: vabs.f32 s1, s1 diff --git a/llvm/test/CodeGen/ARM/fadds.ll b/llvm/test/CodeGen/ARM/fadds.ll index 113f0e29bd1..749690e98d0 100644 --- a/llvm/test/CodeGen/ARM/fadds.ll +++ b/llvm/test/CodeGen/ARM/fadds.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vadd.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vadd.f32 s0, s0, s1 +; CORTEXA9: vadd.f32 s0, s1, s0 diff --git a/llvm/test/CodeGen/ARM/fdivs.ll b/llvm/test/CodeGen/ARM/fdivs.ll index 9af1217de1d..0c314957929 100644 --- a/llvm/test/CodeGen/ARM/fdivs.ll +++ b/llvm/test/CodeGen/ARM/fdivs.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vdiv.f32 s0, s1, s0 ; CORTEXA9: test: -; CORTEXA9: vdiv.f32 s0, s0, s1 +; CORTEXA9: vdiv.f32 s0, s1, s0 diff --git a/llvm/test/CodeGen/ARM/fmacs.ll b/llvm/test/CodeGen/ARM/fmacs.ll index c4ceca9828b..f8b47b5bac0 100644 --- a/llvm/test/CodeGen/ARM/fmacs.ll +++ b/llvm/test/CodeGen/ARM/fmacs.ll @@ -21,4 +21,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vmul.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vmla.f32 s0, s1, s2 +; CORTEXA9: vmla.f32 s2, s1, s0 diff --git a/llvm/test/CodeGen/ARM/fmscs.ll b/llvm/test/CodeGen/ARM/fmscs.ll index 19359a1ae6b..7a70543dee6 100644 --- a/llvm/test/CodeGen/ARM/fmscs.ll +++ b/llvm/test/CodeGen/ARM/fmscs.ll @@ -19,6 +19,6 @@ entry: ; NFP0: vnmls.f32 s2, s1, s0 ; CORTEXA8: test: -; CORTEXA8: vnmls.f32 s1, s2, s0 +; CORTEXA8: vnmls.f32 s2, s1, s0 ; CORTEXA9: test: -; CORTEXA9: vnmls.f32 s0, s1, s2 +; CORTEXA9: vnmls.f32 s2, s1, s0 diff --git a/llvm/test/CodeGen/ARM/fmuls.ll b/llvm/test/CodeGen/ARM/fmuls.ll index bfafd20c860..ef4e3e52818 100644 --- a/llvm/test/CodeGen/ARM/fmuls.ll +++ b/llvm/test/CodeGen/ARM/fmuls.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vmul.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vmul.f32 s0, s0, s1 +; CORTEXA9: vmul.f32 s0, s1, s0 diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll index 897fb1af01c..01e3a922f65 100644 --- a/llvm/test/CodeGen/ARM/shifter_operand.ll +++ b/llvm/test/CodeGen/ARM/shifter_operand.ll @@ -36,8 +36,8 @@ entry: ; lsl #2 is free ; A9: test3: -; A9: ldr r1, [r1, r2, lsl #2] ; A9: ldr r0, [r0, r2, lsl #2] +; A9: ldr r1, [r1, r2, lsl #2] %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 %tmp3 = inttoptr i32 %tmp2 to i32* |
