diff options
| author | Adam Nemet <anemet@apple.com> | 2015-07-17 18:14:19 +0000 |
|---|---|---|
| committer | Adam Nemet <anemet@apple.com> | 2015-07-17 18:14:19 +0000 |
| commit | 5a6d5bc17b385293e3337b9f2082151594f972f9 (patch) | |
| tree | 68b84e4d2228fbee8e8578f0092305e9cd9e78c4 /llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll | |
| parent | 4cb0ba311a91e7374290d4faddbc7d018b130095 (diff) | |
| download | bcm5719-llvm-5a6d5bc17b385293e3337b9f2082151594f972f9.tar.gz bcm5719-llvm-5a6d5bc17b385293e3337b9f2082151594f972f9.zip | |
Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift."
This reverts commit r242500.
It broke some internal tests and Matthias asked me to revert it while he
is investigating.
llvm-svn: 242553
Diffstat (limited to 'llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll index 79e8e68e2f5..c3de07e03b6 100644 --- a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false ; dependency) when it isn't dependent on last CPSR defining instruction. ; rdar://8928208 @@ -7,10 +7,8 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { entry: ; CHECK-LABEL: t1: -; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2 -; CHECK-CORTEX-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 -; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0 -; CHECK-SWIFT-NEXT: mul [[REG:(r[0-9]+)]], r2, r3 +; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 +; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]] %0 = mul nsw i32 %a, %b %1 = mul nsw i32 %c, %d @@ -23,7 +21,8 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { entry: ; CHECK-LABEL: t2: - br label %while.body + %tobool7 = icmp eq i32* %ptr2, null + br i1 %tobool7, label %while.end, label %while.body while.body: ; CHECK: while.body @@ -56,7 +55,8 @@ while.end: define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize { entry: ; CHECK-LABEL: t3: - br label %while.body + %tobool7 = icmp eq i32* %ptr2, null + br i1 %tobool7, label %while.end, label %while.body while.body: ; CHECK: while.body |
