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| author | Matthias Braun <matze@braunis.de> | 2015-07-17 01:44:31 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2015-07-17 01:44:31 +0000 |
| commit | 2d8315f8066bbce201e9b2c28b7d24915dcbe5f0 (patch) | |
| tree | 6de810000cfdd7af9f988349786d0d911cf9932f /llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll | |
| parent | fb2398d0c43405a6b654c80560e38fb3ccd134b9 (diff) | |
| download | bcm5719-llvm-2d8315f8066bbce201e9b2c28b7d24915dcbe5f0.tar.gz bcm5719-llvm-2d8315f8066bbce201e9b2c28b7d24915dcbe5f0.zip | |
ARM: Enable MachineScheduler and disable PostRAScheduler for swift.
This is mostly done to disable the PostRAScheduler which optimizes for
instruction latencies which isn't a good fit for out-of-order
architectures. This also allows to leave out the itinerary table in
swift in favor of the SchedModel ones.
This change leads to performance improvements/regressions by as much as
10% in some benchmarks, in fact we loose 0.4% performance over the
llvm-testsuite for reasons that appear to be unknown or out of the
compilers control. rdar://20803802 documents the investigation of
these effects.
While it is probably a good idea to perform the same switch for the
other ARM out-of-order CPUs, I limited this change to swift as I cannot
perform the benchmark verification on the other CPUs.
Differential Revision: http://reviews.llvm.org/D10513
llvm-svn: 242500
Diffstat (limited to 'llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll index c3de07e03b6..79e8e68e2f5 100644 --- a/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/llvm/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false ; dependency) when it isn't dependent on last CPSR defining instruction. ; rdar://8928208 @@ -7,8 +7,10 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { entry: ; CHECK-LABEL: t1: -; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 -; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 +; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2 +; CHECK-CORTEX-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 +; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0 +; CHECK-SWIFT-NEXT: mul [[REG:(r[0-9]+)]], r2, r3 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]] %0 = mul nsw i32 %a, %b %1 = mul nsw i32 %c, %d @@ -21,8 +23,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { entry: ; CHECK-LABEL: t2: - %tobool7 = icmp eq i32* %ptr2, null - br i1 %tobool7, label %while.end, label %while.body + br label %while.body while.body: ; CHECK: while.body @@ -55,8 +56,7 @@ while.end: define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize { entry: ; CHECK-LABEL: t3: - %tobool7 = icmp eq i32* %ptr2, null - br i1 %tobool7, label %while.end, label %while.body + br label %while.body while.body: ; CHECK: while.body |
