[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only.

Other opcodes shouldn't be CSE'd until we can be sure debug info quality won't
be degraded.

This change also improves the IRTranslator so that in most places, but not all,
it creates constants using the MIRBuilder directly instead of first creating a
new destination vreg and then creating a constant. By doing this, the
buildConstant() method can just return the vreg of an existing G_CONSTANT
instead of having to create a COPY from it.

I measured a 0.2% improvement in compile time and a 0.9% improvement in code
size at -O0 ARM64.

Compile time:
Program                                        base   cse    diff
test-suite...ark/tramp3d-v4/tramp3d-v4.test     9.04   9.12  0.8%
test-suite...Mark/mafft/pairlocalalign.test     2.68   2.66 -0.7%
test-suite...-typeset/consumer-typeset.test     5.53   5.51 -0.4%
test-suite :: CTMark/lencod/lencod.test         5.30   5.28 -0.3%
test-suite :: CTMark/Bullet/bullet.test        25.82  25.76 -0.2%
test-suite...:: CTMark/ClamAV/clamscan.test     6.92   6.90 -0.2%
test-suite...TMark/7zip/7zip-benchmark.test    34.24  34.17 -0.2%
test-suite :: CTMark/SPASS/SPASS.test           6.25   6.24 -0.1%
test-suite...:: CTMark/sqlite3/sqlite3.test     1.66   1.66 -0.1%
test-suite :: CTMark/kimwitu++/kc.test         13.61  13.60 -0.0%
Geomean difference                                          -0.2%

Code size:
Program                                        base     cse      diff
test-suite...-typeset/consumer-typeset.test    1315632  1266480 -3.7%
test-suite...:: CTMark/ClamAV/clamscan.test    1313892  1297508 -1.2%
test-suite :: CTMark/lencod/lencod.test        1439504  1423112 -1.1%
test-suite...TMark/7zip/7zip-benchmark.test    2936980  2904172 -1.1%
test-suite :: CTMark/Bullet/bullet.test        3478276  3445460 -0.9%
test-suite...ark/tramp3d-v4/tramp3d-v4.test    8082868  8033492 -0.6%
test-suite :: CTMark/kimwitu++/kc.test         3870380  3853972 -0.4%
test-suite :: CTMark/SPASS/SPASS.test          1434904  1434896 -0.0%
test-suite...Mark/mafft/pairlocalalign.test    764528   764528   0.0%
test-suite...:: CTMark/sqlite3/sqlite3.test    782092   782092   0.0%
Geomean difference                                              -0.9%

Differential Revision: https://reviews.llvm.org/D60580

llvm-svn: 358369

4 files changed, 12 insertions, 26 deletions

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
index 8e83bc4d9e4..ca41f4577d7 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
@@ -120,7 +120,6 @@ body:             |
     ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
     %2(s16) = G_CTLZ %1
 
-    ; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
     ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]]
     ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]]
@@ -167,7 +166,6 @@ body:             |
     ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
     %2(s8) = G_CTLZ_ZERO_UNDEF %1
 
-    ; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
     ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
     ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]]
     ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]]
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
index 462351ef19f..a14f89f06f6 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
@@ -126,7 +126,6 @@ body:             |
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
@@ -180,7 +179,6 @@ body:             |
     ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY $r0
@@ -234,7 +232,6 @@ body:             |
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
@@ -288,7 +285,6 @@ body:             |
     ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY $r0
@@ -422,7 +418,6 @@ body:             |
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
@@ -479,7 +474,6 @@ body:             |
     ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY $r0
@@ -536,7 +530,6 @@ body:             |
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
@@ -593,7 +586,6 @@ body:             |
     ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
     ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
     ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
     ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY $r0
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index 3f4f1186ae0..b413130558e 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -1738,8 +1738,8 @@ body:             |
     ; SOFT-DEFAULT: BL{{.*}} &__ltsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
     ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO2]]
     ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
     ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
     ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
@@ -1798,8 +1798,8 @@ body:             |
     ; SOFT-DEFAULT: BL{{.*}} &__unordsf2, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0
     ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO2]]
     ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
     ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
     ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
@@ -2662,8 +2662,8 @@ body:             |
     ; SOFT-DEFAULT: BL{{.*}} &__ltdf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
     ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO2]]
     ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
     ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
     ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
@@ -2738,8 +2738,8 @@ body:             |
     ; SOFT-DEFAULT: BL{{.*}} &__unorddf2, {{.*}}, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0
     ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO2:%[0-9]+]]:_(s32) = COPY [[ZERO]]
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO2]]
     ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
     ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
     ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
index a7d83d549b8..8ab1f8767b4 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
@@ -107,8 +107,7 @@ body:             |
     ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
     ; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
     ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]]
-    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
+    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
     ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1)
     ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
     ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
@@ -145,20 +144,17 @@ body:             |
     ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
     ; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
     ; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]]
-    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
+    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
     ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1)
     ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
-    ; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]]
-    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
+    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
     ; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1)
     %0(p0) = COPY $r0
     %1(s64) = G_LOAD %0(p0) :: (load 8, align 1)
     G_STORE %1(s64), %0(p0) :: (store 8, align 1)
 
     ; CHECK: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4)
-    ; CHECK-NEXT: [[OFFCOPY:%[0-9]+]]:_(s32) = COPY [[OFF]]
-    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFCOPY]]
+    ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
     ; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4)
     ; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4)
     ; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]