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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-13 15:52:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-13 15:52:21 +0000 |
| commit | 0a04a062500e2c6d5b92b59c545db3f45e9daffe (patch) | |
| tree | f7d822819221ac8eefc2f1ff606d35465558f601 /llvm/test/CodeGen/ARM/GlobalISel | |
| parent | 5af9cf042f21d6b044f8925b581a8f089d739bc5 (diff) | |
| download | bcm5719-llvm-0a04a062500e2c6d5b92b59c545db3f45e9daffe.tar.gz bcm5719-llvm-0a04a062500e2c6d5b92b59c545db3f45e9daffe.zip | |
GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR
llvm-svn: 368705
Diffstat (limited to 'llvm/test/CodeGen/ARM/GlobalISel')
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index 5c9fbf1fe21..616299c3c09 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -446,6 +446,17 @@ define i32 @test_shufflevector_s32_v2s32(i32 %arg) { ret i32 %res } +define i32 @test_shufflevector_s32_s32_s32(i32 %arg) { +; CHECK-LABEL: name: test_shufflevector_s32_s32_s32 +; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0 +; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF +; CHECK: [[VEC:%[0-9]+]]:_(s32) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], shufflemask(0) + %vec = insertelement <1 x i32> undef, i32 %arg, i32 0 + %shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <1 x i32> zeroinitializer + %res = extractelement <1 x i32> %shuffle, i32 0 + ret i32 %res +} + define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) { ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $r0 |
