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| author | Diana Picus <diana.picus@linaro.org> | 2017-07-13 11:09:34 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-07-13 11:09:34 +0000 |
| commit | c4521756425c46d4aa64f0268502401e2fc83e1f (patch) | |
| tree | 64ac142a961e7681180b8e3cb8d5015660a274cd /llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll | |
| parent | 50b2dd336e398a4516a693a4356fa1c942783e9f (diff) | |
| download | bcm5719-llvm-c4521756425c46d4aa64f0268502401e2fc83e1f.tar.gz bcm5719-llvm-c4521756425c46d4aa64f0268502401e2fc83e1f.zip | |
[ARM] GlobalISel: Support G_BR
This boils down to not crashing in reg bank select due to the lack of
register operands on this instruction, and adding some tests. The
instruction selection is already covered by the TableGen'erated code.
llvm-svn: 307904
Diffstat (limited to 'llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll index 4c498ff6ca9..b763b48c474 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll @@ -420,3 +420,14 @@ entry: %r = select i1 %cond, i32* %a, i32* %b ret i32* %r } + +define arm_aapcscc void @test_br() { +; CHECK-LABEL: test_br +; CHECK: [[LABEL:.L[[:alnum:]_]+]]: +; CHECK: b [[LABEL]] +entry: + br label %infinite + +infinite: + br label %infinite +} |
