From c4521756425c46d4aa64f0268502401e2fc83e1f Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Thu, 13 Jul 2017 11:09:34 +0000 Subject: [ARM] GlobalISel: Support G_BR This boils down to not crashing in reg bank select due to the lack of register operands on this instruction, and adding some tests. The instruction selection is already covered by the TableGen'erated code. llvm-svn: 307904 --- llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll') diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll index 4c498ff6ca9..b763b48c474 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll @@ -420,3 +420,14 @@ entry: %r = select i1 %cond, i32* %a, i32* %b ret i32* %r } + +define arm_aapcscc void @test_br() { +; CHECK-LABEL: test_br +; CHECK: [[LABEL:.L[[:alnum:]_]+]]: +; CHECK: b [[LABEL]] +entry: + br label %infinite + +infinite: + br label %infinite +} -- cgit v1.2.3