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authorJim Grosbach <grosbach@apple.com>2011-11-14 23:03:21 +0000
committerJim Grosbach <grosbach@apple.com>2011-11-14 23:03:21 +0000
commit3e2c6f380c5700d17370a4bfa998acffeed1c32d (patch)
tree233060be861c2984ea971849474856156a3c32b4 /llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
parent0201a4c2d361efa54155c482d250bdc869bd472f (diff)
downloadbcm5719-llvm-3e2c6f380c5700d17370a4bfa998acffeed1c32d.tar.gz
bcm5719-llvm-3e2c6f380c5700d17370a4bfa998acffeed1c32d.zip
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
Diffstat (limited to 'llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll')
-rw-r--r--llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
index 3c9216cde7b..42b14914814 100644
--- a/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
+++ b/llvm/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s
; Should trigger a NEON store.
-; CHECK: vstr.64
+; CHECK: vstr
define void @f_0_12(i8* nocapture %c) nounwind optsize {
entry:
call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)
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