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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-17 09:45:35 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-17 09:45:35 +0000 |
| commit | e4d12bb2d61eb5d7401d6cab2f990e43d1081f2c (patch) | |
| tree | c2da94c06ae2a778fedacdde3847a58ad06d116b /llvm/test/CodeGen/AMDGPU | |
| parent | a0220b0570f8825d8cbe36930756502491c0e31b (diff) | |
| download | bcm5719-llvm-e4d12bb2d61eb5d7401d6cab2f990e43d1081f2c.tar.gz bcm5719-llvm-e4d12bb2d61eb5d7401d6cab2f990e43d1081f2c.zip | |
[DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT
If we are only extracting vector elements via EXTRACT_VECTOR_ELT(s) we may be able to use SimplifyDemandedVectorElts to avoid unnecessary vector ops.
Differential Revision: https://reviews.llvm.org/D49262
llvm-svn: 337258
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll | 48 |
1 files changed, 19 insertions, 29 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll index 0e5ac1e6add..31199b47e20 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll @@ -480,38 +480,28 @@ bb7: ; preds = %bb4, %bb1 ; GCN-LABEL: {{^}}multi_same_block: -; GCN-DAG: v_mov_b32_e32 v[[VEC0_ELT0:[0-9]+]], 0x41880000 -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41900000 -; GCN-DAG: v_mov_b32_e32 v[[VEC0_ELT2:[0-9]+]], 0x41980000 -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a00000 -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a80000 -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41b00000 -; GCN-DAG: s_load_dword [[ARG:s[0-9]+]] -; IDXMODE-DAG: s_add_i32 [[ARG_ADD:s[0-9]+]], [[ARG]], -16 - -; MOVREL-DAG: s_add_i32 m0, [[ARG]], -16 -; MOVREL: v_movreld_b32_e32 v[[VEC0_ELT0]], 4.0 -; GCN-NOT: m0 - -; IDXMODE: s_set_gpr_idx_on [[ARG_ADD]], dst -; IDXMODE: v_mov_b32_e32 v[[VEC0_ELT0]], 4.0 +; GCN: s_load_dword [[ARG:s[0-9]+]] + +; MOVREL: v_mov_b32_e32 v{{[0-9]+}}, 0x41900000 +; MOVREL: v_mov_b32_e32 v{{[0-9]+}}, 0x41b0cccd +; MOVREL: s_waitcnt +; MOVREL: s_add_i32 m0, [[ARG]], -16 +; MOVREL: v_movreld_b32_e32 v{{[0-9]+}}, 4.0 +; MOVREL: v_movreld_b32_e32 v{{[0-9]+}}, -4.0 +; MOVREL: s_mov_b32 m0, -1 + + +; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 0x41900000 +; IDXMODE: s_waitcnt +; IDXMODE: s_add_i32 [[ARG]], [[ARG]], -16 +; IDXMODE: s_set_gpr_idx_on [[ARG]], dst +; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 4.0 ; IDXMODE: s_set_gpr_idx_off - -; GCN: v_mov_b32_e32 v[[VEC0_ELT2]], 0x4188cccd -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x4190cccd -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x4198cccd -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a0cccd -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a8cccd -; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41b0cccd - -; MOVREL: v_movreld_b32_e32 v[[VEC0_ELT2]], -4.0 - -; IDXMODE: s_set_gpr_idx_on [[ARG_ADD]], dst -; IDXMODE: v_mov_b32_e32 v[[VEC0_ELT2]], -4.0 +; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 0x41b0cccd +; IDXMODE: s_set_gpr_idx_on [[ARG]], dst +; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, -4.0 ; IDXMODE: s_set_gpr_idx_off -; PREGFX9: s_mov_b32 m0, -1 -; GFX9-NOT: s_mov_b32 m0 ; GCN: ds_write_b32 ; GCN: ds_write_b32 ; GCN: s_endpgm |
