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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-09 16:06:37 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-09 16:06:37 +0000 |
| commit | d8409b178ed4b5af52eb82190b5d1c846ed8b63c (patch) | |
| tree | 2614fd79a1cbf590db9cfdc09eace725914a79f7 /llvm/test/CodeGen/AMDGPU | |
| parent | 9ede7c03956376105130421c786e1360e948b290 (diff) | |
| download | bcm5719-llvm-d8409b178ed4b5af52eb82190b5d1c846ed8b63c.tar.gz bcm5719-llvm-d8409b178ed4b5af52eb82190b5d1c846ed8b63c.zip | |
AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loads
llvm-svn: 371416
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir | 53 |
1 files changed, 51 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir index 1370ed3fa5f..d129383817b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s --- | define amdgpu_kernel void @load_global_v8i32_non_uniform(<8 x i32> addrspace(1)* %in) { @@ -65,6 +65,9 @@ define amdgpu_kernel void @extload_global_i8_to_i32_uniform() { ret void } define amdgpu_kernel void @extload_constant_i16_to_i32_uniform() { ret void } define amdgpu_kernel void @extload_global_i16_to_i32_uniform() { ret void } + define amdgpu_kernel void @load_constant_i32_uniform_align4() {ret void} + define amdgpu_kernel void @load_constant_i32_uniform_align2() {ret void} + define amdgpu_kernel void @load_constant_i32_uniform_align1() {ret void} declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone } @@ -586,3 +589,49 @@ body: | %0:_(p4) = COPY $sgpr0_sgpr1 %1:_(s32) = G_LOAD %0 :: (load 2, addrspace 1, align 2) ... + +--- +name: load_constant_i32_uniform_align4 +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: load_constant_i32_uniform_align4 + ; CHECK: %0:sgpr(p4) = COPY $sgpr0_sgpr1 + ; CHECK: %1:sgpr(s32) = G_LOAD %0(p4) :: (load 4, addrspace 4) + %0:_(p4) = COPY $sgpr0_sgpr1 + %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 4) +... + +--- +name: load_constant_i32_uniform_align2 +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + ; CHECK-LABEL: name: load_constant_i32_uniform_align2 + ; CHECK: %0:sgpr(p4) = COPY $sgpr0_sgpr1 + ; CHECK: %2:vgpr(p4) = COPY %0(p4) + ; CHECK: %1:vgpr(s32) = G_LOAD %2(p4) :: (load 4, align 2, addrspace 4) + + %0:_(p4) = COPY $sgpr0_sgpr1 + %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 2) +... + +--- +name: load_constant_i32_uniform_align1 +legalized: true + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + + ; CHECK-LABEL: name: load_constant_i32_uniform_align1 + ; CHECK: %0:sgpr(p4) = COPY $sgpr0_sgpr1 + ; CHECK: %2:vgpr(p4) = COPY %0(p4) + ; CHECK: %1:vgpr(s32) = G_LOAD %2(p4) :: (load 4, align 1, addrspace 4) + %0:_(p4) = COPY $sgpr0_sgpr1 + %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 1) +... |
