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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-19 04:11:17 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-19 04:11:17 +0000 |
| commit | bffbeecb44a4a727784b1777e56fe8c9a0fea3fb (patch) | |
| tree | 2c07d5808cfa006597f6b336925e2a6a11af82ac /llvm/test/CodeGen/AMDGPU | |
| parent | 4f663a63677d71fbeaeab29d716525fd8cfe1477 (diff) | |
| download | bcm5719-llvm-bffbeecb44a4a727784b1777e56fe8c9a0fea3fb.tar.gz bcm5719-llvm-bffbeecb44a4a727784b1777e56fe8c9a0fea3fb.zip | |
AMDGPU/GlobalISel: RegBankSelect llvm.amdgcn.ds.swizzle
llvm-svn: 372297
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir new file mode 100644 index 00000000000..54c3a5009ca --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir @@ -0,0 +1,21 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: ds_swizzle_s +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0 + + ; CHECK-LABEL: name: ds_swizzle_s + ; CHECK: liveins: $sgpr0 + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), [[COPY1]](s32), 0 + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), %0, 0 + +... |
