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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-16 19:09:04 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-16 19:09:04 +0000 |
| commit | b95ddd7ceac7011f456fc576e60d391a6e13c312 (patch) | |
| tree | 23e474daee394ca5270ec8b4df7a953e3b27872f /llvm/test/CodeGen/AMDGPU | |
| parent | eb65cda986c34b9b50a1f0d46d4277cafc05c2a4 (diff) | |
| download | bcm5719-llvm-b95ddd7ceac7011f456fc576e60d391a6e13c312.tar.gz bcm5719-llvm-b95ddd7ceac7011f456fc576e60d391a6e13c312.zip | |
AMDGPU: Remove llvm.AMDGPU.cube intrinsic
llvm-svn: 295359
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/cube.ll | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll (renamed from llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll) | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll | 22 |
4 files changed, 22 insertions, 24 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/cube.ll b/llvm/test/CodeGen/AMDGPU/cube.ll index 9b512c439b0..3c126a42fdd 100644 --- a/llvm/test/CodeGen/AMDGPU/cube.ll +++ b/llvm/test/CodeGen/AMDGPU/cube.ll @@ -6,9 +6,6 @@ declare float @llvm.amdgcn.cubesc(float, float, float) #0 declare float @llvm.amdgcn.cubetc(float, float, float) #0 declare float @llvm.amdgcn.cubema(float, float, float) #0 -declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0 - - ; GCN-LABEL: {{^}}cube: ; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} @@ -29,18 +26,5 @@ define void @cube(<4 x float> addrspace(1)* %out, float %a, float %b, float %c) ret void } -; GCN-LABEL: {{^}}legacy_cube: -; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} -; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} -; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} -; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} -; GCN: _store_dwordx4 -define void @legacy_cube(<4 x float> addrspace(1)* %out, <4 x float> %abcx) #1 { - %cube = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %abcx) - store <4 x float> %cube, <4 x float> addrspace(1)* %out - ret void -} - attributes #0 = { nounwind readnone } attributes #1 = { nounwind } - diff --git a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll b/llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll index 78b88122229..b5a0de95acf 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll @@ -22,7 +22,7 @@ main_body: %tmp12 = insertelement <4 x float> %tmp11, float %tmp7, i32 1 %tmp13 = insertelement <4 x float> %tmp12, float %tmp10, i32 2 %tmp14 = insertelement <4 x float> %tmp13, float 1.000000e+00, i32 3 - %tmp15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp14) + %tmp15 = call <4 x float> @llvm.r600.cube(<4 x float> %tmp14) %tmp16 = extractelement <4 x float> %tmp15, i32 0 %tmp17 = extractelement <4 x float> %tmp15, i32 1 %tmp18 = extractelement <4 x float> %tmp15, i32 2 @@ -44,7 +44,7 @@ main_body: } ; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0 +declare <4 x float> @llvm.r600.cube(<4 x float>) #0 ; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #0 diff --git a/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll b/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll index 461caf5b5d2..e2143ff85b7 100644 --- a/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll +++ b/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll @@ -10,7 +10,7 @@ main_body: %tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 1 %tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 2 %tmp8 = insertelement <4 x float> %tmp7, float %tmp4, i32 3 - %tmp9 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp8) + %tmp9 = call <4 x float> @llvm.r600.cube(<4 x float> %tmp8) %tmp10 = extractelement <4 x float> %tmp9, i32 0 %tmp11 = extractelement <4 x float> %tmp9, i32 1 %tmp12 = extractelement <4 x float> %tmp9, i32 2 @@ -45,7 +45,7 @@ main_body: } ; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0 +declare <4 x float> @llvm.r600.cube(<4 x float>) #0 ; Function Attrs: readnone declare float @fabs(float) #0 diff --git a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll index 974823e8b8c..d71f872637b 100644 --- a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll @@ -586,7 +586,19 @@ IF67: ; preds = %LOOP65 %tmp449 = insertelement <4 x float> %tmp448, float %tmp445, i32 1 %tmp450 = insertelement <4 x float> %tmp449, float %tmp447, i32 2 %tmp451 = insertelement <4 x float> %tmp450, float %tmp194, i32 3 - %tmp452 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp451) + + %tmp451.x = extractelement <4 x float> %tmp451, i32 0 + %tmp451.y = extractelement <4 x float> %tmp451, i32 1 + %tmp451.z = extractelement <4 x float> %tmp451, i32 2 + %cubetc = call float @llvm.amdgcn.cubetc(float %tmp451.x, float %tmp451.y, float %tmp451.z) + %cubesc = call float @llvm.amdgcn.cubesc(float %tmp451.x, float %tmp451.y, float %tmp451.z) + %cubema = call float @llvm.amdgcn.cubema(float %tmp451.x, float %tmp451.y, float %tmp451.z) + %cubeid = call float @llvm.amdgcn.cubeid(float %tmp451.x, float %tmp451.y, float %tmp451.z) + %tmp452.0 = insertelement <4 x float> undef, float %cubetc, i32 0 + %tmp452.1 = insertelement <4 x float> %tmp452.0, float %cubesc, i32 1 + %tmp452.2 = insertelement <4 x float> %tmp452.1, float %cubema, i32 2 + %tmp452 = insertelement <4 x float> %tmp452.2, float %cubeid, i32 3 + %tmp453 = extractelement <4 x float> %tmp452, i32 0 %tmp454 = extractelement <4 x float> %tmp452, i32 1 %tmp455 = extractelement <4 x float> %tmp452, i32 2 @@ -1841,9 +1853,6 @@ declare float @llvm.amdgcn.rsq.f32(float) #0 declare <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 ; Function Attrs: nounwind readnone -declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0 - -; Function Attrs: nounwind readnone declare float @llvm.fabs.f32(float) #0 ; Function Attrs: nounwind readnone @@ -1863,6 +1872,11 @@ declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0 ; Function Attrs: nounwind readnone declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0 +declare float @llvm.amdgcn.cubeid(float, float, float) #0 +declare float @llvm.amdgcn.cubesc(float, float, float) #0 +declare float @llvm.amdgcn.cubetc(float, float, float) #0 +declare float @llvm.amdgcn.cubema(float, float, float) #0 + attributes #0 = { nounwind readnone } attributes #1 = { nounwind } |

