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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-06-25 16:17:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-06-25 16:17:48 +0000 |
| commit | b1cc4f52ff0fbec69064ad72a3527dc0406ac03b (patch) | |
| tree | 7f61fa7b3db597712eff5715b5144ef38704daa4 /llvm/test/CodeGen/AMDGPU | |
| parent | 1c79e4e9592a7543f5ecf302c6d1e59dfea58671 (diff) | |
| download | bcm5719-llvm-b1cc4f52ff0fbec69064ad72a3527dc0406ac03b.tar.gz bcm5719-llvm-b1cc4f52ff0fbec69064ad72a3527dc0406ac03b.zip | |
AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptr
Note a normal select test is not currently possible because this
relies on input registers tracked in SIMachineFunctionInfo which
are not currently serializable in MIR, but this does work end-to-end
from the IR.
llvm-svn: 335490
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg.segment.ptr.mir | 19 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir | 14 |
2 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg.segment.ptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg.segment.ptr.mir new file mode 100644 index 00000000000..7ae60773986 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg.segment.ptr.mir @@ -0,0 +1,19 @@ +# XFAIL: * +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN + +# FIXME: This requires additional context for what input registers are special inputs not present in MIR. + +--- + +name: kernarg_segment_Ptr +legalized: true +regBankSelected: true + +body: | + bb.0: + %0:vgpr(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr) + %1:sgpr(s32) = G_LOAD %0 :: (load 4) + %2:vgpr(p1) = G_IMPLICIT_DEF + G_STORE %1, %2 :: (store 4) +... +--- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir new file mode 100644 index 00000000000..78fd2fd79a1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir @@ -0,0 +1,14 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: kernarg_segment_ptr +legalized: true + +body: | + bb.0: + ; CHECK-LABEL: name: kernarg_segment_ptr + ; CHECK: [[INT:%[0-9]+]]:sgpr(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr) + %2:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr) +... |
