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| author | Tom Stellard <tstellar@redhat.com> | 2018-06-22 02:34:29 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-06-22 02:34:29 +0000 |
| commit | 9a6535718ef98397a6c910a920fb1472b9e5ecb0 (patch) | |
| tree | 03a2e07b59c373d53884fdf7592f284fdcb45cac /llvm/test/CodeGen/AMDGPU | |
| parent | 7712ee8891dc9b57c2a5e3f159a83dad63ee9f16 (diff) | |
| download | bcm5719-llvm-9a6535718ef98397a6c910a920fb1472b9e5ecb0.tar.gz bcm5719-llvm-9a6535718ef98397a6c910a920fb1472b9e5ecb0.zip | |
AMDGPU/GlobalISel: legalize and select 32-bit G_SITOFP
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48195
llvm-svn: 335316
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir | 36 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir | 14 |
2 files changed, 50 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir new file mode 100644 index 00000000000..42fc095985a --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir @@ -0,0 +1,36 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN + +--- | + define amdgpu_kernel void @sitofp(i32 addrspace(1)* %global0) {ret void} +... +--- + +name: sitofp +legalized: true +regBankSelected: true + +# GCN-LABEL: name: sitofp +body: | + bb.0: + liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4 + + ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 + %0:sgpr(s32) = COPY $sgpr0 + + ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr0 + + %2:vgpr(s64) = COPY $vgpr3_vgpr4 + + ; sitofp s + ; GCN: V_CVT_F32_I32_e64 [[SGPR]], 0, 0 + %3:vgpr(s32) = G_SITOFP %0 + + ; sitofp v + ; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0 + %4:vgpr(s32) = G_SITOFP %1 + + G_STORE %3, %2 :: (store 4 into %ir.global0) + G_STORE %4, %2 :: (store 4 into %ir.global0) +... +--- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir new file mode 100644 index 00000000000..649f8903cd1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir @@ -0,0 +1,14 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- +name: test_sitofp_f32_to_i32 +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: test_sitofp_f32_to_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_SITOFP %0 +... |
