diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-11 18:54:20 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-09-11 18:54:20 +0000 |
| commit | 537bd3b906f9f3126ddef03bbcdcdb756edac4f9 (patch) | |
| tree | 0a805a0fd661f258cbee25160a475efe6c90bd25 /llvm/test/CodeGen/AMDGPU | |
| parent | d4f3723c561fc5d1bea0350aa3ad2c7c7937bf38 (diff) | |
| download | bcm5719-llvm-537bd3b906f9f3126ddef03bbcdcdb756edac4f9.tar.gz bcm5719-llvm-537bd3b906f9f3126ddef03bbcdcdb756edac4f9.zip | |
AMDGPU: Allow coldcc calls
llvm-svn: 312936
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/calling-conventions.ll | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll index 677147b6f4e..9bf94a1f2da 100644 --- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll +++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll @@ -43,3 +43,37 @@ define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) { %add = fadd half %arg0, 1.0 ret half %add } + +; GCN-LABEL: {{^}}fastcc: +; GCN: v_add_f32_e32 v0, 4.0, v0 +define fastcc float @fastcc(float %arg0) #0 { + %add = fadd float %arg0, 4.0 + ret float %add +} + +; GCN-LABEL: {{^}}coldcc: +; GCN: v_add_f32_e32 v0, 4.0, v0 +define coldcc float @coldcc(float %arg0) #0 { + %add = fadd float %arg0, 4.0 + ret float %add +} + +; GCN-LABEL: {{^}}call_coldcc: +; GCN: v_mov_b32_e32 v0, 1.0 +; GCN: s_swappc_b64 +define amdgpu_kernel void @call_coldcc() #0 { + %val = call float @coldcc(float 1.0) + store float %val, float addrspace(1)* undef + ret void +} + +; GCN-LABEL: {{^}}call_fastcc: +; GCN: v_mov_b32_e32 v0, 1.0 +; GCN: s_swappc_b64 +define amdgpu_kernel void @call_fastcc() #0 { + %val = call float @fastcc(float 1.0) + store float %val, float addrspace(1)* undef + ret void +} + +attributes #0 = { nounwind noinline }
\ No newline at end of file |
